DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim and Specification Status
The Examiner acknowledges the amendments to claims 1 and 20 in the Applicant’s response dated 7 August 2026. The claim amendments have been addressed below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-7, 9-11 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Shiqun Gu et al. (US 9,368,450 B1; hereinafter “Gu”) in view of Tetsuyuki Tsuchida (US 2019/0287930 A1; hereinafter “Tsuchida”) in further view of Chih-Wei Wu et al. (US 2021/0098421 A1; hereinafter Wu).
Regarding Claim 1, Gu teaches a semiconductor package comprising:
a first redistribution layer (904, Fig. 9, column 15, lines 53-55 describe a redistribution layer 904) that includes a first insulating layer (844, Fig. 9, column 16, line 44 describes a dielectric layer 844) and a first conductive pattern in the first insulating layer (945, Fig. 9, column 16, line 46 describes an interconnect 945 in the first insulating layer 844);
a connection module on an upper surface of the first redistribution layer (210, Fig. 9, column 16, lines 34-36 describe a bridge 210 on an upper surface of the first redistribution layer 904 through layer 606);
a core that extends around the connection module on the upper surface of the first redistribution layer (606, Fig. 9, column 15, lines 53-56 describe an encapsulation layer 606 extending around connection module 210 on the upper surface of the first redistribution layer 904 wherein core 606 may comprise an epoxy or resin material);
a through via extended in the core (803, Fig. 9, column 15, lines 53-56 describe a first via 803 extended in core 606);
a second insulating layer on the core (840, Fig. 9, column 16, lines 18-20 describe a dielectric layer 840 on the core 606), wherein a portion of the second insulating layer is in the through via (840, Fig. 9, column 16, lines 18-20 describe wherein second insulating layer 840 is located within the cavity created by the vias 803);
a second redistribution layer on an upper surface of the core (SRL, annotated Fig. 10, depicts a second redistribution layer on an upper surface of the core 606 wherein column 17, lines 16-25 describe wherein the package 1000 as shown in Fig. 10 may be coupled to the base 900 as shown in Fig. 9), wherein the second redistribution layer includes a third insulating layer (1050, Fig. 10, column 17, lines 38-43 describes a non-conducting fill layer 1050), a second conductive pattern (1022, Fig. 10, column 17, lines 26-27 describe interconnect pillars 1022), and a via pad (611, Fig. 9, column 15, lines 55-57 describe a first pad 611); and
a first semiconductor chip (1002, Fig. 10, column 17, lines 18-20 describe a first semiconductor die 1002) and a second semiconductor chip on an upper surface of the second redistribution layer (1004, Fig. 10, column 17, lines 18-20 describe a second semiconductor die 1004 wherein the first semiconductor chip 1002 and second semiconductor chip 1004 are disposed on an upper surface of the second redistribution layer),
wherein the first semiconductor chip and the second semiconductor chip are spaced apart from each other (1002 and 1004, Fig. 10 depicts wherein the first semiconductor chip 1002 and second semiconductor chip 1004 are spaced apart from each other),
wherein the via pad is in contact with the through via (611, Fig. 9, column 16, lines 9-10 describe wherein the via pad 611 is coupled to the through via 803), and
wherein the first semiconductor chip and the second semiconductor chip are electrically connected to each other through the connection module (210, Fig. 10 depicts wherein the bridge 210 electrically connects the first semiconductor chip 1002 to the second semiconductor chip through the redistribution layer as described by the components in column 5, lines 9-13).
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Gu fails to explicitly disclose wherein the core is a glass core; and wherein the second conductive pattern and the via pad are in the third insulating layer.
However, Tsuchida teaches a similar semiconductor device wherein the core is a glass core (10, Fig. 10, para [0058] describes a glass plate 10 with a through hole); and wherein the second conductive pattern (73, Fig. 10, para [0124] describes a third wiring layer 73) and the via pad (71, Fig. 10, para [0124] describes a first wiring layer 71 wherein para [0130] describes the first wiring layer 71 has a pad portion in contact with third wiring pattern 73) are in the third insulating layer (63, Fig. 10, para [0124] describes a third insulation layer 63 wherein the via pad portion of the first wiring layer 71 and the second conductive pattern 73 are disposed in the third insulating layer 63).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Gu with Tsuchida to further disclose a semiconductor package wherein through vias are disposed in a core that is comprised of glass in order to provide the further advantage of providing a wiring substrate for through vias to pass through that can achieve a high degree of smoothness as compared to glass epoxy resin thus allowing ultra-fine wiring and further providing for excellent high-speed transmission (Tsuchida, para [0004]-para [0007]) and to further disclose wherein a via pad portion and a second conductive pattern are disposed in a same insulating layer in order to provide the well-known advantage of enabling electrical insulation between device components preventing leakage current and potential short circuits between adjacent components of the device.
The combination of Gu and Tsuchida fail to explicitly disclose wherein a first underfill is disposed between the first semiconductor chip and the second redistribution layer.
However, Wu teaches a similar semiconductor package, wherein a first underfill (250, Fig. 3, para [0055] describes an underfill layer 250) is disposed between the first semiconductor chip (200A, Fig. 1F, para [0038] describes a device package 200A that may be a semiconductor chip) and the second redistribution layer (150, Fig. 1F, para [0038] describes a second redistribution layer 150 wherein the underfill layer 250 is disposed between the second redistribution structure 150 and the first semiconductor chip 200A).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Gu and Tsuchida with Wu to further disclose a semiconductor package wherein a first underfill is disposed between a first semiconductor chip and a second redistribution layer in order to provide the well-known advantage of filling the space between connection components of a semiconductor device and a redistribution layer preventing current leakage which may result in undesirable device characteristics and providing the advantage of enabling structural support surrounding the connection components.
Regarding Claim 2, the combination of Gu, Tsuchida and Wu disclose the semiconductor package of claim 1, wherein the through via includes a lower contact portion (Gu, LPC, annotated Fig. 9 depicts a lower contact portion LPC) and an upper contact portion (Gu, UPC, annotated Fig. 9 depicts an upper contact portion UPC),
wherein the lower contact portion is on a lower surface of the glass core (Gu, LPC, annotated Fig. 9 depicts wherein the lower contact portion LPC is on a lower surface of the core 606),
wherein the lower surface of the glass core and the upper surface of the glass core are opposite to each other (Gu, CUS and CLS, annotated Fig. 9 depicts wherein a lower surface of the core CLS and upper surface of the core CUS are opposite to each other),
wherein the upper contact portion is in contact with the via pad (Gu, UPC and 611, annotated Fig. 9 depicts wherein the upper contact portion UPC and via pad 611 are in contact with each other), and
wherein a width of the lower contact portion in a horizontal direction parallel with the upper surface of the first redistribution layer is greater than a width of the upper contact portion in the horizontal direction (Gu, UPC and LPC, annotated Fig. 9 depicts wherein the lower contact portion extends on the lower surface of the core CLS in a horizontal direction parallel with the upper surface of the first redistribution layer 904 resulting in a lower contact portion LPC with a width greater than a width of the upper contact portion UPC).
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Regarding Claim 4, the combination of Gu, Tsuchida and Wu disclose the semiconductor package of claim 2, wherein the upper contact portion is completely overlapped by the via pad in a vertical direction perpendicular to the upper surface of the first redistribution layer (Gu, 611 and UPC, annotated Fig. 9 depicts wherein the via pad 611 completely overlaps the upper contact portion UPC in a vertical direction perpendicular to the upper surface of the first redistribution layer 904).
Regarding Claim 5, the combination of Gu, Tsuchida and Wu disclose the semiconductor package of claim 2, wherein the width of the upper contact portion is about 60 micrometers (μm) or less in the horizontal direction (Gu, column 8, lines 19-28 describe wherein the vias of the first embodiment, similar to the embodiment in Fig. 9, may have a width of about 10 microns or less wherein a resulting upper contact portion UPC from annotated Fig. 9 would have a resulting width of 10 microns or micrometers or less in the horizontal direction).
Regarding Claim 6, the combination of Gu, Tsuchida and Wu disclose the semiconductor package of claim 1, wherein the via pad includes a metal layer (Tsuchida, 71, Fig. 10, para [0131] describes wherein the wiring layer 71 contains copper wherein the via pad of the wiring layer 71 as described in para [0130] would constitute a copper metal layer).
Regarding Claim 7, the combination of Gu, Tsuchida and Wu disclose the semiconductor package of claim 1, wherein a thickness of the glass core in a vertical direction perpendicular to the upper surface of the first redistribution layer is greater than a thickness of the connection module in the vertical direction (Gu, 606 and 210, Fig. 9 depicts wherein the core 606, in combination with the glass core 10 of Tsuchida, may be disposed between a part of the redistribution layer 904 and connection module 210 in a vertical direction perpendicular to the upper surface of the first redistribution layer 904 resulting in a thickness of the core 606 being greater than a thickness of the connection module 210).
Regarding Claim 9, the combination of Gu, Tsuchida and Wu disclose the semiconductor package of claim 1, wherein a distance between an outer surface of the through via and an outer surface of the portion of the second insulating layer in the through via in a horizontal direction parallel with the upper surface of the first redistribution layer is about 20 micrometers (μm) or less (Gu, column 8, lines 19-28 describe wherein the vias of the first embodiment, similar to the embodiment in Fig. 9, may have a width of about 10 microns or less wherein a resulting distance between an outer surface of the through via and an outer surface of the portion of the second insulating layer 840 in the through via in a horizontal direction parallel with the upper surface of the first redistribution layer 904 would be less than 20 micrometers).
Regarding Claim 10, the combination of Gu, Tsuchida and Wu disclose the semiconductor package of claim 1, wherein the connection module includes silicon (Si) (Gu, 210, Fig. 9, column 5, lines 28-29 describe wherein the connection module 210 may comprise a silicon bridge).
Regarding Claim 11, the combination of Gu, Tsuchida and Wu disclose the semiconductor package of claim 1, further comprising a first connection member on a lower surface of the first redistribution layer (284, Fig. 3, column 9, lines 38-42 describe solder balls 284 on a lower surface of redistribution layer 308 wherein column 15 lines 46-52 describe wherein redistribution layer 904 of base 900 in Fig. 9 may be a further embodiment of redistribution layer 308 from Fig. 3), wherein the first connection member is electrically connected to a package substrate (205 and 284, Fig. 3, column 9, lines 38-42 describe wherein solder balls 284 are coupled to a printed circuit board 205 wherein a printed circuit board may represent a package substrate).
Regarding Claim 20, Gu teaches a semiconductor package comprising:
a first redistribution layer (904, Fig. 9, column 15, lines 53-55 describe a redistribution layer 904) that includes a first insulating layer (844, Fig. 9, column 16, line 44 describes a dielectric layer 844) and a first conductive pattern in the first insulating layer (945, Fig. 9, column 16, line 46 describes an interconnect 945 in the first insulating layer 844);
a connection module on an upper surface of the first redistribution layer (210, Fig. 9, column 16, lines 34-36 describe a bridge 210 on an upper surface of the first redistribution layer 904 through layer 606);
a core that extends around the connection module on the upper surface of the first redistribution layer (606, Fig. 9, column 15, lines 53-56 describe an encapsulation layer 606 extending around connection module 210 on the upper surface of the first redistribution layer 904 wherein core 606 may comprise an epoxy or resin material), wherein the core includes a through via (803, Fig. 9, column 15, lines 53-56 describe a first via 803 extended in core 606);
a second insulating layer that extend around the glass core (840, Fig. 9, column 16, lines 18-20 describe a dielectric layer 840 that extends around a surface of the core 606), wherein a portion of the second insulating layer is inside the through via (840, Fig. 9, column 16, lines 18-20 describe wherein second insulating layer 840 is located within the cavity created by the vias 803);
a second redistribution layer on an upper surface of the core (SRL, annotated Fig. 10, depicts a second redistribution layer on an upper surface of the core 606 wherein column 17, lines 16-25 describe wherein the package 1000 as shown in Fig. 10 may be coupled to the base 900 as shown in Fig. 9), wherein the second redistribution layer includes a third insulating layer (1050, Fig. 10, column 17, lines 38-43 describes a non-conducting fill layer 1050), a second conductive pattern (1022, Fig. 10, column 17, lines 26-27 describe interconnect pillars 1022), and a via pad (611, Fig. 9, column 15, lines 55-57 describe a first pad 611); and
a first semiconductor chip (1002, Fig. 10, column 17, lines 18-20 describe a first semiconductor die 1002) and a second semiconductor chip that are spaced apart from each other on an upper surface of the second redistribution layer (1004, Fig. 10, column 17, lines 18-20 describe a second semiconductor die 1004 wherein the first semiconductor chip 1002 and second semiconductor chip 1004 are disposed on an upper surface of the second redistribution layer wherein Fig. 10 depicts the first semiconductor chip 1002 and second semiconductor chip 1004 as being spaced apart from each other),
wherein the via pad is in contact with an upper contact portion of the through via (611, annotated Fig. 9, column 16, lines 9-10 describe wherein the via pad 611 is coupled to an upper contact portion UPC of the through via 803),
wherein the first semiconductor chip and the second semiconductor chip are electrically connected to each other through the connection module (210, Fig. 10 depicts wherein the bridge 210 electrically connects the first semiconductor chip 1002 to the second semiconductor chip through the redistribution layer as described by the components in column 5, lines 9-13),
wherein the through via includes a lower contact portion that is electrically connected to the first conductive pattern (LPC, annotated Fig. 9 depicts a lower contact portion LPC of the through via that is electrically connected to the first conductive pattern 945 through interconnect 943), and
wherein a width of the lower contact portion in a horizontal direction parallel with the upper surface of the first redistribution layer is greater than a width of the upper contact portion in the horizontal direction (UPC and LPC, annotated Fig. 9 depicts wherein the lower contact portion extends on the lower surface of the core CLS in a horizontal direction parallel with the upper surface of the first redistribution layer 904 resulting in a lower contact portion LPC with a width greater than a width of an upper contact portion UPC).
Gu fails to explicitly disclose wherein the core is a glass core; and wherein the second conductive pattern and the via pad are in the third insulating layer; and wherein the via pad includes a metal layer.
However, Tsuchida teaches a similar semiconductor device wherein the core is a glass core (10, Fig. 10, para [0058] describes a glass plate 10 with a through hole); and
wherein the second conductive pattern (73, Fig. 10, para [0124] describes a third wiring layer 73) and the via pad (71, Fig. 10, para [0124] describes a first wiring layer 71 wherein para [0130] describes the first wiring layer 71 has a pad portion in contact with third wiring pattern 73) are in the third insulating layer (63, Fig. 10, para [0124] describes a third insulation layer 63 wherein the via pad portion of the first wiring layer 71 and the second conductive pattern 73 are disposed in the third insulating layer 63); and
wherein the via pad includes a metal layer (71, Fig. 10, para [0131] describes wherein the wiring layer 71 contains copper wherein the via pad of the wiring layer 71 as described in para [0130] would constitute a copper metal layer).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Gu with Tsuchida to further disclose a semiconductor package wherein through vias are disposed in a core that is comprised of glass in order to provide the further advantage of providing a wiring substrate for through vias to pass through that can achieve a high degree of smoothness as compared to glass epoxy resin thus allowing ultra-fine wiring and further providing for excellent high-speed transmission (Tsuchida, para [0004]-para [0007]) and to further disclose wherein a via pad portion and a second conductive pattern are disposed in a same insulating layer in order to provide the well-known advantage of enabling electrical insulation between device components preventing leakage current and potential short circuits between adjacent components of the device and to further disclose wherein the via pad includes a metal layer in order to provide the advantage of enabling a via pad to be electrically conductive in order to route electrical signals within a device (Tsuchida, para [0130]).
The combination of Gu and Tsuchida fail to explicitly disclose wherein a first underfill is disposed between the first semiconductor chip and the second redistribution layer.
However, Wu teaches a similar semiconductor package, wherein a first underfill (250, Fig. 3, para [0055] describes an underfill layer 250) is disposed between the first semiconductor chip (200A, Fig. 1F, para [0038] describes a device package 200A that may be a semiconductor chip) and the second redistribution layer (150, Fig. 1F, para [0038] describes a second redistribution layer 150 wherein the underfill layer 250 is disposed between the second redistribution structure 150 and the first semiconductor chip 200A).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Gu and Tsuchida with Wu to further disclose a semiconductor package wherein a first underfill is disposed between a first semiconductor chip and a second redistribution layer in order to provide the well-known advantage of filling the space between connection components of a semiconductor device and a redistribution layer preventing current leakage which may result in undesirable device characteristics and providing the advantage of enabling structural support surrounding the connection components.
Claims 8 is rejected under 35 U.S.C. 103 as being unpatentable over Shiqun Gu et al. (US 9,368,450 B1; hereinafter “Gu”) in view of Tetsuyuki Tsuchida (US 2019/0287930 A1; hereinafter “Tsuchida”) in further view of Chih-Wei Wu et al. (US 2021/0098421 A1; hereinafter Wu) and in further view Srinivas V. Pietambaram et al. (US 2020/0312767 A1; hereinafter “Pietambaram”).
Regarding Claim 8, the combination of Gu, Tsuchida and Wu discloses all the limitations of claim 7.
The combination of Gu, Tsuchida and Wu fails to explicitly disclose the semiconductor package of claim 7, wherein a difference between the thickness of the glass core and the thickness of the connection module is about 15 micrometers (μm) to about 30 μm.
However, Pietambaram teaches a similar semiconductor package wherein a difference between the thickness of the glass core and the thickness of the connection module is about 15 micrometers (μm) to about 30 μm (124 and 110, Fig. 1F, para [0044] describes a glass substrate 110 and a bridge die 124 representing a connection module wherein the connection module 124 may have a Z-height in a thickness direction that is about 96 percent the thickness height of the glass core wherein Tsuchida discloses a glass core 10 height of approximately 500 μm in para [0233] therefore upon combining Pietambaram with Gu, Tsuchida and Wu, a connection module height that is 96 percent the thickness of the glass core 110 and 10, being 500 μm, results in a height of the connection module being 480 μm resulting in a different between the two thicknesses of about 20 μm falling within the prescribed range of about 15 μm to 30 μm).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Gu, Tsuchida and Wu with Pietambaram to further disclose a semiconductor package wherein a difference between a thickness of a glass core and a thickness of a connection module is about 15 μm to about 30 μm in order to provide the advantage of enabling a glass core and a connection module to have a height ratio sufficient to enable a bump to be disposed on an upper surface of a connection module resulting in a substantially planar surface between the upper surface of the bump and the upper surface of the glass core (Pietambaram, para [0042]).
Response to Arguments
Applicant’s arguments with respect to claims 1-2, 4-11 and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ALEXANDER MICHAEL MILLER/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
