DETAILED ACTION
Election/Restrictions
Claims 12-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to nonelected group II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 04/01/2026.
Claims 1-11 and 21-29 are pending in the current application.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 05/01/2024 and 07/09/2025 are compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a) because they fail to show, in Fig. 3, the “Fin spacers 45” as described in paragraph [0027] of the specification. Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
In the specification, [0027] discloses in the last line “Fin spacers 45 are also formed.” However, “Fin spacers 45” were not found in any of the drawings nor is the feature discussed or referenced in the rest of the specification.
In the specification, [0065] discloses in lines 3-4 “Upper transistors U and the respective lower transistor 10U.” It appears that the upper transistors should be labeled “10U” and the lower transistors should be labeled “10L”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 24 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 24 states “The method of claim 21 further comprising forming a second transistor, wherein the first transistor overlaps the first transistor” which renders the claim indefinite. The claim is indefinite because it is unclear whether any overlap exists or which transistor is on top of which.
It appears the intended meaning, based on the overall claim set and consistency with claims 2 and 3, that the claim language was intended to state “wherein the first transistor overlaps the second transistor” and so will be interpreted in this manner.
Claim 24 further states “forming a second high-k dielectric layer on the second interfacial layer, wherein the first interfacial layer and the first high-k dielectric layer comprise a second dipole dopant” which renders the claim indefinite. The claim is indefinite because it appears that the claim language was intended to state “wherein the second interfacial layer and the second high-k dielectric layer comprise a second dipole dopant.”
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-9, 21-24 and 27-28 are rejected under 35 U.S.C. 103 as being unpatentable over FRANCO et al. (US 20200176446 A1), hereinafter “Franco,” in view of LIN et al. (US 20240387286 A1), hereinafter “Lin.”
Re: Claim 1, Franco discloses a method (Fig. 25) comprising:
forming a first transistor (Fig. 8: transistor 100) comprising:
forming a first semiconductor nanostructure (Fig. 8: transistor 100; ¶0026: forming a p-channel metal-oxide-semiconductor gate stack at nm scales);
forming a first interfacial layer … the first semiconductor nanostructure (Fig. 8: IL 120; See Fig. 25, step 210);
depositing a first dipole film on the first interfacial layer (Fig. 8: 1st dip. 130; Fig. 25, step 220);
depositing a first high-k dielectric layer on the first dipole film (Fig. 8: High-K 140; Fig. 25, step 240); and
depositing a first gate electrode on the first high-k dielectric layer (Fig. 8: work function metal 150; Fig. 24 shows a gate electrode; Fig. 25, step 250).
However, Franco does not specifically disclose wherein the first interfacial layer is encircling the semiconductor nanostructure.
In a similar field of endeavor having to do with dipole doping of GAA transistor layers while maintaining a low thermal budget, Lin discloses … encircling… (¶0081: at operation 10, the interfacial layer 270 is deposited on the first, i.e., second/lower transistor hGAA structure 215).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application, to have used the manufacturing techniques disclose in Franco to create a CFET incorporating gate-all-around transistors as disclosed in Lin in order to create improved multi-VT transistors having reduced thickness, reduced leakage, and lower thermal budget while also minimizing the equivalent oxide thickness (EOT) penalty (See Lin, ¶0014).
Re: Claim 2, the combination of Franco in view Lin discloses the method of claim 1.
Franco also discloses further comprising forming a second transistor, wherein the first transistor overlaps the second transistor (See Fig. 24; ¶0023: CMOS device in a first layer, stacked onto one or more transistors in a second layer; ¶0144: A pMOS gate stack … applied in a sequential 3D stack of CMOS logic tiers (an exemplary 3D stack of Seq3D over CMOS is illustrated in FIG. 24)),
However, Franco does clearly disclose and the forming the second transistor comprises: forming a second semiconductor nanostructure; forming a second interfacial layer encircling the second semiconductor nanostructure; depositing a second high-k dielectric layer on the second interfacial layer; depositing a second dipole film on the second high-k dielectric layer; driving-in a dipole dopant in the second dipole film into the second high-k dielectric layer; removing the second dipole film; depositing a second gate electrode on the second high-k dielectric layer;
In a similar field of endeavor, Lin discloses and the forming the second transistor comprises (Fig. 1B: second transistor 215, i.e., lower transistor; ¶0067: the vertically stacked superlattice structure 260 comprises one or more horizontal gate-all-around (hGAA) structures 215, 255 on the substrate 202):
forming a second semiconductor nanostructure (Fig. 1B: second/lower transistor 215 has nanosheet channel layers 230);
forming a second interfacial layer encircling the second semiconductor nanostructure (¶0081: at operation 10, the interfacial layer 270 is deposited on the first, i.e., second/lower transistor hGAA structure 215);
depositing a second high-k dielectric layer on the second interfacial layer (¶0084: at operation 12, the high-K dielectric layer 272 is conformally deposited on the interfacial layer 270);
depositing a second dipole film on the second high-k dielectric layer (¶0077: deposit first p-type dipole layer on high-k dielectric layer; ¶0087: p-type dipole layer 274);
driving-in a dipole dopant in the second dipole film into the second high-k dielectric layer (¶0078: operation 50 includes annealing to drive atoms from the dipole layer into the high-k dielectric layer to form an annealed high-k dielectric layer; ¶0121: operation 50 includes a rapid thermal process (RTP));
removing the second dipole film (¶0078: At operation 52, the method 100 includes etching the vertically stacked superlattice structure to remove each of the first p-type dipole layer); and
depositing a second gate electrode on the second high-k dielectric layer (¶0123: After operation 52, the method 100 can include any post-processing operations for semiconductor manufacturing known to the skilled artisan, e.g., gate electrode metal deposition on the high-k dielectric layer).
A person of ordinary skill in the art would combine Lin’s CFET overlapping structure (which uses a traditional dipole-on-high-k flow on the lower tier) with Franco’s explicit teaching that high-temperature drive-in/reliability anneals damaged lower-tier or BEOL devices (See Franco, ¶¶0009, 0023-0024, and 0027).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to apply Franco’s simplified low-thermal-budget dipole-on-IL process only to the upper transistor while keeping Lin’s traditional flow on the lower transistor in order to protect the already-formed lower tier while still achieving independent multi-Vt tuning in a dense 3D CFET with reduced thickness, reduced leakage, and lower thermal budget (See Lin, ¶0014).
Re: Claim 3, the combination of Franco in view of Lin discloses the method of claim 1.
Franco also discloses further comprising forming a second transistor, wherein the first transistor overlaps the second transistor (See Fig. 24; ¶0023: CMOS device in a first layer, stacked onto one or more transistors in a second layer; ¶0144: A pMOS gate stack can be applied in a sequential 3D stack of CMOS logic tiers (See FIG. 24). In other words, Franco discloses the process below may be performed on a first transistor and a second transistor on an upper tier.), and the forming the second transistor comprises:
forming a second semiconductor nanostructure (Fig. 8: transistor 100);
forming a second interfacial layer encircling the second semiconductor nanostructure (Fig. 25: 210 Forming IL; See claim 1 for Lin’s teaching of “encircling”);
depositing a second dipole film on the second interfacial layer (Fig. 25: 220 Depositing Dip. Layer);
depositing a second high-k dielectric layer on the second dipole film (Fig. 25: 240 depositing High-K); and
depositing a second gate electrode on the second high-k dielectric layer (Fig. 25: 250 Depositing WF-metal).
Re: Claim 5, the combination of Franco in view Lin discloses the method of claim 1.
Franco further discloses wherein at a time when the first gate electrode is deposited, the first dipole film remains between the first interfacial layer and the first high-k dielectric layer (Fig. 25: first dipole deposited at 220 between IL layer 210 and high-k layer 240 and remains part of the structure until deposition of the WF-metal gate electrode material which is deposited at step 250).
Re: Claim 6, the combination of Franco in view Lin discloses the method of claim 1.
Franco further discloses wherein in an entire period of time starting at a first time the first dipole film is deposited and ending at a second time the first gate electrode has been formed, no drive-in process is performed to drive dipole dopants in the first dipole film into the first interfacial layer (Fig. 25: first dipole is deposited at 220 and remains until first WF-metal gate electrode is deposited at step 250 without including a drive-in process.; ¶0027: a functional reliable pMOS gate stack can be obtained according to various embodiments without use of a high temperature reliability anneal after the gate stack deposition.).
Re: Claim 7, the combination of Franco in view Lin discloses the method of claim 1.
Franco further discloses wherein until a time after the first gate electrode has been deposited, no removal process is performed to remove the first dipole film (Fig. 25: first dipole deposited at 220 between IL layer 210 and high-k layer 240 and remains part of the structure until deposition of the WF-metal gate electrode material which is deposited at step 250 without removal of the first dipole film.).
Re: Claim 8, the combination of Franco in view Lin discloses the method of claim 1.
Franco further disclosers wherein a peak dipole dopant of the first dipole film is in middle between the first interfacial layer and the first high-k dielectric layer (Fig. 8: 1st dip. 130 between, i.e., middle, the 1st interfacial and 1st high-k layer; ¶0086: first dipole forming capping layer 130 has thickness below 1nm. In other words, the 1st dip. layer is extremely thin so any dopants, charges, or dipole-forming species within it have their peak concentration or effect located within the middle of this thin intervening film, i.e., in the middle between the IL and high-k.).
Re: Claim 9, the combination of Franco in view Lin discloses the method of claim 1.
Franco further discloses wherein the first dipole film has a thickness smaller than about 1Å (¶0086: first dipole forming capping layer 130 has thickness below 1nm).
Re: Claim 21, Franco discloses a method (Fig. 25) comprising:
forming a first transistor comprising (Fig. 8: transistor 100):
forming a first source region and a first drain region on opposing sides, and joined to, a first semiconductor nanostructure (Fig. 24 shows S/D regions on the side of a first semiconductor nanostructure); and
forming a first gate stack … the first semiconductor nanostructure, wherein the first gate stack is formed by processes comprising:
forming a first interfacial layer (Fig. 8: IL 120; See Fig. 25, step 210);
forming a first high-k dielectric layer on the first interfacial layer (Fig. 8: High-K 140; Fig. 25, step 240; Fig. 8 shows, given the BRI, High-K 140 on IL 120),
wherein processes of forming the first interfacial layer and the first high-k dielectric layer comprise doping a first dipole dopant (Fig. 8: 1st dip. 130; Fig. 25, step 220), so that a first peak concentration of the first dipole dopant is in middle between the first interfacial layer and the first high-k dielectric layer (Fig. 8: 1st dip. 130 between, i.e., middle, the 1st interfacial and 1st high-k layer; ¶0086: first dipole forming capping layer 130 has thickness below 1nm. In other words, the 1st dip. layer is extremely thin so any dopants, charges, or dipole-forming species within it have their peak concentration or effect located within the middle of this thin intervening film, i.e., in the middle between the IL and high-k.); and
forming a first gate electrode on the first high-k dielectric layer (Fig. 8: work function metal 150; Fig. 24 shows a gate electrode; Fig. 25, step 250; ¶0093: at least one work function metal 150 can be a portion of a gate electrode stack).
However, Franco does not specifically disclose wherein the first interfacial layer is encircling the semiconductor nanostructure.
In a similar field of endeavor having to do with dipole doping of GAA transistor layers while maintaining a low thermal budget, Lin discloses … encircling… (¶0081: at operation 10, the interfacial layer 270 is deposited on the first, i.e., second/lower transistor hGAA structure 215).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application, to have used the manufacturing techniques disclose in Franco to create a CFET incorporating gate-all-around transistors as disclosed in Lin in order to create improved multi-VT transistors having reduced thickness, reduced leakage, and lower thermal budget while also minimizing the equivalent oxide thickness (EOT) penalty (See Lin, ¶0014).
Re: Claim 22, the combination of Franco in view of Lin discloses the method of claim 21.
Franco further discloses wherein the first dipole dopant is diffused, so that the first interfacial layer joins the first high-k dielectric layer, and the first peak concentration is at an interface of the first interfacial layer and the first high-k dielectric layer (Fig. 8: 1st dip. 130 between, i.e., middle, the 1st interfacial and 1st high-k layer; ¶0086: first dipole forming capping layer 130 has thickness below 1nm. In other words, the 1st dip. layer is extremely thin so any dopants, charges, or dipole-forming species within it have their peak concentration or effect located within the middle of this thin intervening film, i.e., at an interface of the first IL and high-k.).
Re: Claim 23, the combination of Franco in view of Lin discloses the method of claim 21.
Franco also discloses further comprising depositing a dipole film comprising the first dipole dopant, wherein the dipole film is deposited between the first interfacial layer and the first high-k dielectric layer (Fig. 8: 130 dipole film comprising the first dipole dopant is between IL and high-k).
Re: Claim 24, the combination of Franco in view of Lin discloses the method of claim 21.
Franco also discloses further comprising forming a second transistor, wherein the first transistor overlaps the first transistor (Note: See 112b section above for interpretation; See Fig. 24; ¶0023: CMOS device in a first layer, stacked onto one or more transistors in a second layer; ¶0144: A pMOS gate stack can be applied in a sequential 3D stack of CMOS logic tiers (See FIG. 24). In other words, Franco discloses the process below may be performed on a first transistor and a second transistor on an upper tier.), and wherein the forming the second transistor comprises:
forming a second semiconductor nanostructure (Fig. 8: transistor 100; See Fig. 24: second nanostructure); and
forming a second gate stack encircling the second semiconductor nanostructure (Fig. 24: second gate stack; See claim 21 for Lin’s teaching of “encircling”), wherein the forming the second gate stack comprises:
forming a second interfacial layer (Fig. 8: IL 120; Fig. 25: 210 Forming IL; Fig. 24: second nanostructure);
forming a second high-k dielectric layer on the second interfacial layer (Fig. 8: high-k 140; Fig. 25: 240 depositing high-k; Fig. 24: second nanostructure), wherein the first interfacial layer and the first high-k dielectric layer comprise a second dipole dopant (Fig. 8: Dip. 130; Fig. 25: 220 depositing Dip.; Fig. 24: second nanostructure); and
forming a second gate electrode on the second high-k dielectric layer (Fig. 8: work function metal 150; Fig. 24: second gate in stack; Fig. 25, step 250; ¶0093: work function metal 150 can be a portion of a gate electrode stack), …
However, Franco does not specifically disclose wherein a second peak concentration of the second dipole dopant is at an interface between the second high-k dielectric layer and the second gate electrode.
Lin further discloses wherein a second peak concentration of the second dipole dopant is at an interface between the second high-k dielectric layer and the second gate electrode (Fig. 1: step 10: deposit IL, Step 12: deposit high-k; step 14: deposit Dipole. In other words, Lin discloses depositing the dipole layer on the high-k so any dopants, charges, or dipole-forming species within it have their peak concentration or effect located at an interface between the second high-k layer and the second gate electrode).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to apply Franco’s simplified low-thermal-budget dipole-on-IL process only to the upper transistor while keeping Lin’s traditional flow on the lower transistor in order to protect the already-formed lower tier while still achieving independent multi-Vt tuning in a dense 3D CFET with reduced thickness, reduced leakage, and lower thermal budget (See Lin, ¶0014).
Re: Claim 27, Franco discloses a method (Fig. 25) comprising:
forming a lower transistor comprising a first gate stack (Fig. 8: transistor 100; Fig. 24: lower transistor and upper transistor; ¶0093: work function metal 150 can be a portion of a gate electrode stack), wherein the first gate stack is formed by processes comprising:
forming a first interfacial layer (Fig. 8: IL 120; See Fig. 25, step 210);
depositing a first high-k dielectric layer on the first interfacial layer (Fig. 8: High-K 140; Fig. 25, step 240; Fig. 8 shows, given the BRI, High-K 140 is on IL 120);
forming a first gate electrode on the first high-k dielectric layer (Fig. 8: WF-metal 150; Fig. 24 shows gate electrodes; ¶0093: work function metal 150 can be a portion of a gate electrode stack); and
…
forming an upper transistor overlapping the lower transistor (Fig. 24: upper and lower transistor), wherein the upper transistor comprises a second gate stack that is formed by processes comprising (Fig. 24 shows gate electrodes; ¶0023: CMOS device in a first layer, stacked onto one or more transistors in a second layer; ¶0144: A pMOS gate stack can be applied in a sequential 3D stack of CMOS logic tiers (See FIG. 24). In other words, Franco discloses the process below may be performed on a first transistor and a second transistor on an upper tier.):
forming a second interfacial layer (Fig. 8: IL 120; Fig. 25: 210 Forming IL; Fig. 24: second nanostructure);
depositing a second high-k dielectric layer on the second interfacial layer (Fig. 8: high-k 140, given the BRI, High-K 140 is on IL 120; Fig. 25: 240 depositing high-k; Fig. 24: second nanostructure), wherein the second interfacial layer and the second high-k dielectric layer comprise a second dipole dopant (Fig. 8: IL 120 and high-k 140 comprise dipole dopant 130), and a second peak concentration of the second dipole dopant is in middle between the second interfacial layer and the second high-k dielectric layer (Fig. 8: 1st dip. 130 between, i.e., middle, the 1st interfacial and 1st high-k layer; ¶0086: first dipole forming capping layer 130 has thickness below 1nm. In other words, the 1st dip. layer is extremely thin so any dopants, charges, or dipole-forming species within it have their peak concentration or effect located within the middle of this thin intervening film, i.e., at an interface of the first IL and high-k.); and
forming a second gate electrode on the second high-k dielectric layer (Fig. 8: work function metal 150 on high-k 140; Fig. 24 shows a gate electrode; Fig. 25, step 250; ¶0093: at least one work function metal 150 can be a portion of a gate electrode stack).
However, Franco does not disclose performing a doping process, so that the first high-k dielectric layer and the first gate electrode comprise a first dipole dopant, and a first peak concentration of the first dipole dopant is at an interface between the first high-k dielectric layer and the first gate electrode; and
In a similar field of endeavor, Lin discloses performing a doping process, so that the first high-k dielectric layer and the first gate electrode comprise a first dipole dopant (Fig. 1: step 10: deposit IL, Step 12: deposit high-k; step 14: deposit Dipole.), and a first peak concentration of the first dipole dopant is at an interface between the first high-k dielectric layer and the first gate electrode (Fig. 1: step 10: deposit IL, Step 12: deposit high-k; step 14: deposit Dipole. In other words, Lin discloses depositing the dipole layer on the high-k so any dopants, charges, or dipole-forming species within it have their peak concentration or effect located at an interface between the second high-k layer and the second gate electrode); and
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to apply Franco’s simplified low-thermal-budget dipole-on-IL process only to the upper transistor while keeping Lin’s traditional flow on the lower transistor in order to protect the already-formed lower tier while still achieving independent multi-Vt tuning in a dense 3D CFET with reduced thickness, reduced leakage, and lower thermal budget (See Lin, ¶0014).
Re: Claim 28, the combination of Franco in view of Lin discloses the method of claim 27.
Franco further discloses wherein the lower transistor is formed as having an opposite conductivity type than the upper transistor (Fig. 24: upper and lower transistor; ¶0017: pMOS and nMOS; see ¶0029).
Claims 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over FRANCO et al. (US 20200176446 A1) in view of LIN et al. (US 20240387286 A1) and PARK et al. (US 20230146060 A1), hereinafter “Park.”
Re: Claim 10, the combination of Franco in view Lin discloses the method of claim 1.
Franco also discloses further comprising forming a source/drain region on a side of the first semiconductor nanostructure (Fig. 24 shows S/D regions on the side of a first semiconductor nanostructure), wherein the source/drain region is of n-type (Fig. 16 shows an nMOS gate stack wherein a source/drain region as shown in Fig. 24 would be n-type),
the first gate electrode comprises a … work-function layer (¶0093: at least one work function metal 150 can be a portion of a gate electrode stack),
and the first dipole film comprises an n-type dipole dopant (¶0138: LaSiO is n-type dopant).
However, the combination does not explicitly disclose p-type material.
In a similar field of endeavor, Park teaches p-type (¶0059: in the case where the lower gate insulating layer LGI contains lanthanum (La), an effective work function of the lower gate electrode LGE may be lowered. As a result, a threshold voltage of an NMOS transistor in the first active region AR1 may be lowered. As another example, … the threshold voltage of the NMOS transistor in the first active region AR1 may be increased.; ¶0063: P-type WFM; ¶0142: A dipole-containing layer DPL may be conformally formed on the lower and upper gate insulating layers LGI and UGI. The dipole-containing layer DPL may contain a dipole element.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have selected appropriate work function metal combinations to achieve a desired threshold voltage when designing both P-type and N-type complementary FET’s while also achieving high reliability (See Park, ¶0070 and ¶0149).
Re: Claim 11, the combination of Franco in view Lin discloses the method of claim 1.
Franco also discloses further comprising forming a source/drain region on a side of the first semiconductor nanostructure (Fig. 24 shows S/D regions on the side of a first semiconductor nanostructure),
wherein the source/drain region is of p-type (Fig. 16 shows an pMOS gate stack wherein a source/drain region as shown in Fig. 24 would be p-type), the first gate electrode comprises an … work-function layer (¶0135: one or more work function metals 150, 350), and the first dipole film comprises a p-type dipole dopant (¶0022: first dipole-forming capping layer of the pMOS transistor is Al2O3).
However, the combination does not explicitly disclose n-type material.
In a similar field of endeavor, Park teaches n-type (¶0064: N-type WFM; ¶0142: A dipole-containing layer DPL may be conformally formed on the lower and upper gate insulating layers LGI and UGI. The dipole-containing layer DPL may contain a dipole element.)
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have selected appropriate work function metal combinations to achieve a desired threshold voltage when designing both P-type and N-type complementary FET’s while also achieving high reliability (See Park, ¶0070 and ¶0149).
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over FRANCO et al. (US 20200176446 A1) in view of LIN et al. (US 20240387286 A1) and SON et al. (US 20220037502 A1), hereinafter “Son.”
Re: Claim 25, the combination of Franco in view of Lin discloses the method of claim 21.
However, the combination does not clearly disclose wherein in directions pointing from the middle between the first interfacial layer and the first high-k dielectric layer into the first interfacial layer and the first high-k dielectric layer, concentrations of the first dipole dopant reduce gradually.
In a similar field of endeavor, Son discloses wherein in directions pointing from the middle between the first interfacial layer and the first high-k dielectric layer into the first interfacial layer and the first high-k dielectric layer, concentrations of the first dipole dopant reduce gradually (Fig. 3 shows a peak dipole concentration in the middle layer between a first layer EG, i.e., interfacial layer, and a high-k layer; ¶0039: The second insulating layer IL may be disposed between the first insulating layer EG and the high-k dielectric layer HK.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have applied Son’s annealing process to diffuse a dipole layer positioned between the interfacial layer and the high-k dielectric layer, as taught by Franco, in order to produce a controlled, gradual reduction in dopant concentration in both directions from the middle of the dielectric stack, thereby providing more precise threshold voltage tuning (See Son, ¶¶0066-0067)
Claims 26 and 29 are rejected under 35 U.S.C. 103 as being unpatentable over FRANCO et al. (US 20200176446 A1) in view of LIN et al. (US 20240387286 A1) and YIM et al. (US 20220375935 A1), hereinafter “Yim.”
Re: Claim 26, the combination of Franco in view of Lin discloses the method of claim 21.
Franco also discloses further comprising forming a second transistor at a same level as the first transistor (Fig. 16 shows pMOS and nMOS at same level), wherein the second transistor comprises a second interfacial layer and a second high-k dielectric layer on the second interfacial layer (Fig. 16: IL 320 and high-k 340), and
However, Franco does not disclose wherein the second interfacial layer and the second high-k dielectric layer are free from the first dipole dopant.
In a similar field of endeavor, Yim discloses wherein the second interfacial layer and the second high-k dielectric layer are free from the first dipole dopant (Fig. 5 shows regions R1 and R2, for example. ¶0048: The first dipole layer 20_1 may not be in the second region R2 and the third region R3. The first dipole layer 20_1 may be formed in the first to third regions R1, R2, R3 and then may be removed from the second and third regions R2, R3 or the first dipole layer 20_1 may be selectively formed in the first region R1.).
Yim teaches that in stacked CFET devices it is desirable to differentiate gate stacks of lower and upper transistors (or different regions) by forming dipole layers and then selectively removing them from certain transistors, thereby achieving multi-VT with desired threshold voltages.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have been motivated to apply Yim’s selective removal technique when combining Franco’s dipole film placement directly on the interfacial layer to achieve desired threshold voltages (See Yim, ¶0059 and ¶0062).
Re: Claim 29, the combination of Franco in view of Lin discloses the method of claim 28.
However the combination does not clearly disclose further comprising forming an additional upper transistor comprising an additional interfacial layer and an additional high-k dielectric layer on the additional interfacial layer, wherein the additional interfacial layer and the additional high-k dielectric layer are free from the second dipole dopant therein.
In a similar field of endeavor, Yim discloses further comprising forming an additional upper transistor comprising an additional interfacial layer and an additional high-k dielectric layer on the additional interfacial layer (See Fig. 1; ¶0016: stack CFET1 includes first upper transistor UT1; ¶0017: stack CFET2 includes a second upper transistor UT2 that are stacked in the vertical direction; Fig. 6 shows multiple regions R1, R2, and R3), wherein the additional interfacial layer and the additional high-k dielectric layer are free from the second dipole dopant therein (¶0048: The first dipole layer 20_1 may not be in the second region R2 and the third region R3. The first dipole layer 20_1 may be formed in the first to third regions R1, R2, R3 and then may be removed from the second and third regions R2, R3; ¶0050: The second dipole layer 20_2 may not be in the first region R1 and the third region R3. The second dipole layer 20_2 may be formed in the first to third regions R1, R2, R3 and then may be removed from the first region R1 and the third region R3, or the second dipole layer 20_2 may be selectively formed in the second region R2.).
Yim teaches that in stacked CFET devices it is desirable to differentiate gate stacks of lower and upper transistors (or different regions) by forming dipole layers and then selectively removing them from certain transistors, thereby achieving multi-VT with desired threshold voltages.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have been motivated to apply Yim’s selective removal technique when combining Franco’s dipole film placement directly on the interfacial layer to achieve desired threshold voltages (See Yim, ¶0059 and ¶0062).
Allowable Subject Matter
Claim 4 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Although Franco, Lin, Park, and Yim each disclose certain individual elements relevant to claim 4, none of these references, alone or in combination, teaches the full scope of the claim. Franco teaches the positioning of a dipole-forming layer directly between the interfacial layer and the high-k dielectric but does not disclose forming dipole films on multiple transistors through a same deposition process or selectively removing the dipole film from one transistor while leaving it on another.
Lin discloses the use of a same deposition process for multiple dipole layers and selective removal in a stacked structure; however, its dipole layers are deposited on the high-k dielectric rather than on the interfacial layer, and it does not teach depositing high-k directly on and in contact with the interfacial layer after removal of the dipole film.
Park describes selective removal of a dipole-containing layer and the resulting high-k structure but deposits the dipole layer on top of the high-k dielectric and relies on a drive-in diffusion step, rather than forming the dipole film on the interfacial layer and subsequently depositing high-k directly onto the interfacial layer.
Yim teaches the formation of dipole layers across multiple regions followed by selective removal, yet it does not clearly establish that the dipole films are deposited on the interfacial layers of separate transistors through a same deposition process, nor does it result in high-k being deposited directly on and contacting the interfacial layer after removal.
Accordingly, the prior art fails to teach or suggest the specific combination of:
further comprising forming a second transistor comprising:
forming a second semiconductor nanostructure; forming a second interfacial layer encircling the second semiconductor nanostructure; depositing a second dipole film on the second interfacial layer, wherein the first dipole film and the second dipole film are deposited in a same deposition process; removing the second dipole film; depositing a second high-k dielectric layer over and contacting the second interfacial layer; and depositing a second gate electrode on the second high-k dielectric layer.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
PAO et al. (US 20210391439 A1) – Fig. 1 method is relevant to some of the features claimed in the current application
HSU et al. (US 20220093472 A1) – Figs. 1A and 1B methods are relevant to some of the features claimed in the current application
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/WILLIAM ADROVEL/Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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