DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Summary of the Invention
The invention describes a monolithic Doherty amplifier die fabricated on a wide-bandgap semiconductor substrate (such as GaN or SiC) that integrates both the main and peak amplifiers on a single chip. Between the input network and the output combiner, an isolation structure is formed on the same substrate to block or reduce radio-frequency (RF) coupling that can otherwise cause instability. The isolation structure can take various forms—such as a metal transmission line, a continuous or discontinuous metal layer, or a U-shaped metallic wall—and can include vias connecting it to ground to enhance isolation. This layout allows a compact, on-chip Doherty amplifier design with reduced interference between input and output circuitry. The device can be implemented with GaN-based HEMTs or LDMOS transistors and may include packaging or flip-chip embodiments using conductive pillars for PCB connection.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
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Fig. 2 of Hue et al. reproduced by the examiner for ease of reference.
Claims 1-4, 6-15, 17-20 and 23-25 are rejected under 35 U.S.C. 102(a)(1) as being unpatentable over Hue et al. (US 2022/0021343 A1).
Regarding claim 1,
Claimed feature
Hue Disclosures (Fig. 2 & related)
Substrate with bandgap > 2 eV
GaN, SiC, or other wide-bandgap devices (§0020, §0040, power FETs)
Main & at least one peak amplifier on substrate
Main (220) and Peaking (240′, 240″) amplifiers integrally formed (§0035-§0038)
Input network connected to main & peak inputs
Power splitter 204 feeding both paths (§0047-§0049)
Output combiner on substrate connected to both outputs
Combining node (290) on same die (§0044, §0085).
Isolation structure between input and output networks
Splitter isolation resistors (452-453) and equal-phase branch arrangement providing electrical isolation (§0050-§0055; Figs. 4–5A) which is functionally identical as providing isolation between input and output networks as claimed.
Regarding claim 12, Hue describes same monolithic die as claim 1 and further teaches input combiner (splitter) & matching networks (IMN 222, 242′, 242″) and input combiner branches with pre-amplifiers.
Regarding claim 25, Hue further teaches in Figs. 6–7 & §0090-§0099
Claimed feature
Hue Disclosures (Fig. 2 & related)
the substrate having a first surface
and a second surface
Substrate (201) with first/top & second/bottom surfaces.
A printed circuit board (PCB) one or more conductive pillar structures that protrude from the first surface of the substrate and are electrically connected to the one or more conductive vias through the printed circuit board.
Copper pillars (“wire bonds/pillars 900” or leads 610–620) coupled via conductive vias 348 to PCB 710. Ground connection through conductive flange 630 and PCB coin 715.
Wherein per claims 2 and 13, Hue also teaches that the isolation structure comprises a transmission line (the resistors providing isolation are connected through conductive traces, see Fig. 2) on the substrate, which essentially is continuous segment of a metal layer per claim 3 and 14. Also, since plurality of resistors (resistors 273, 274, 273’, 274’, 273”, 274”, Fig. 2) are forming isolation structures (275, 276, 275’, 276’, 275”, 276”) in Hue, per claim 4 and 15, multiple conductive traces are connecting multiple resistors and as such these conductive traces are discontinuous segment of a metal layer on the substrate (RF [AltContent: textbox (along a length of the lower surface of the isolation structure)]isolation circuits, §0084).
[AltContent: textbox (Lower surface of isolation structure)][AltContent: ][AltContent: textbox (Source ground of main and peak amplifier)][AltContent: ][AltContent: connector][AltContent: ]
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Fig. 3 of Hue et al. annotated by the examiner for ease of reference.
wherein per claims 6 and 17, the isolation structure (resistors 273, 274, 273’, 274’, 273”, 274”, Fig. 2 and metal patches 275, 276, 275’, 276’, 275”, 276” of Fig. 2) comprises an upper surface (planar structure on top of the substrate) and a lower surface (as can be seen in Fig. 3, a ground plane 328), the Doherty amplifier die (200) further comprising: a first via (229) connected between a first portion of the lower surface of the isolation structure and a source ground of the main amplifier (230); and
a second via (251’) connected between a second portion of the lower surface of the isolation structure and a source ground of the at least one peak amplifier (250’).
And per claims 7 and 18, a plurality of additional vias (348 and similar other vias as shown in Fig. 3) between the first via (225) and the second via (251’), wherein respective vias are spaced apart (see Fig. 3) and connected between a plurality of additional portions of the lower surface of the isolation structure and a ground structure connected to the source ground (328) of the main and peak amplifiers (226, 230, 246’, 246”, 250’ and 250”).
And per claims 8 and 19, further, to claim 6, the Doherty amplifier die further comprising: a via connected along a length (horizontal metal traces, as shown in Fig. 3, are along the length of the lower surface) of the lower surface of the isolation structure and a source ground (328) of the main amplifier and the peak amplifier (226, 230, 246’, 246”, 250’ and 250”).
And per claim 9, wherein the input network comprises a main input match network (IMN 222, ISMN 226, Fig. 2) for the main amplifier (226, 230) and a peak input match network (242’, 242”, 248’, 248”) for the peak amplifier (246’, 246” and 250’ and 250”), and an input combiner (204).
And per claims 10 and 23, wherein the main and the at least one peak amplifier are GaN-based High Electron Mobility Transistors, HEMTs (§0027), and per claim 11 and 24, wherein the main and the at least one peak amplifiers are laterally diffused metal oxide semiconductor, LDMOS, transistors (§0027).
And per claim 20, wherein the plurality of components of the input combiner (204) comprises a first shunt capacitor (at the splitter input terminal 405, 505, a first shunt capacitor 410, 510 is electrically coupled between the input terminal 405,505 and a dividing node 409,509 for the three branches 401-403, 501-503. Each splitter branch 401-403, 501-503 can be a three-section branch having an input impedance matching and/or filter section, comprising a series capacitor (although not shown explicitly but for providing DC bias at the gate of each transistors there must be DC block capacitor in series) , a series inductor (520, 530, 540), and a second shunt capacitor (522, 532, 542), see Figs. 4 and 5A, §0058-§0059.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 5, 16, 21 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Hue and further in view of Kamposch (US20210408979) and Lakshminarayan et al. (US20160043039).
Regarding claim 5 and 16, Hue teaches all limitations of claim 1 and further teaches isolation structures in the form metal patches connected to ground through resistive networks. Hue, however, is not explicit about the metal patches to be “U” shaped.
However, in the similar field of endeavor of integration of Doherty amplifier dies in proximity, Lakshminarayan teaches isolation structure 50 has an inverted U-shape conforming to the exterior surfaces of the cover 70 and being directly connected to the first and second ground connectors 35 and 45 on opposite sides of that cover as shown in Fig. 3 (§0037). Kamposch in a similar filed of endeavor discloses one or more portions of the rivet 201 and/or associated isolation structures 405b may vertically protrude from the flange 276 between the RF leads to define an isolation fence. For example, the isolation structure 405b may include a metal segment (e.g., formed from the same material as the leads, rivets, lead frame, and/or flange) that is bent or otherwise provided in a U-shape 405b' so as to vertically protrude between adjacent RF leads to reduce coupling or electromagnetic/RF interference between adjacent RF leads 272, 274 and/or amplifier paths Pl, P2. Such isolation structures 405b may be advantageous in multi-stage RF power amplifier designs with multiple amplifier paths Pl and P2 defining the main and peaking amplifier paths of a packaged Doherty power amplifier (§0087).
It would, therefore, have been obvious to a person of ordinary skill in the art before the effective filing of the invention to follow the well-known teachings of Kamposch or Lakshminarayan of suing U shaped isolation metal structures connected to ground on both bent ends for effective isolation between two interfering RF regions such as the input and output of two separate paths of the main and peak amplifiers of the Doherty amplifier die of Hue. The combination thereby teaching all limitations of claim 5.
Regarding claims 21 and 22, Although Hue is not explicit about a second series inductor and a second series capacitor, it would have been well within the purview of a person of ordinary skill in the art to use a second series inductor (the trace connecting the DC block capacitor to the gate of each of the transistors essentially exhibit inductive reactance) and second series capacitor for extra filtering as well as phase adjustments between the three different branches of the input splitter (combiner). The motivation of doing so is to achieve further flexibility in designing a three-way splitter/combiner as taught by Hue.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAFIZUR RAHMAN whose telephone number is (571)270-0659. The examiner can normally be reached M-F: 10-6.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached on (571) 272-1769. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
/HAFIZUR RAHMAN/Primary Examiner, Art Unit 2843.