DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I (claims 1-13) in the reply filed on 01/16/2026 is acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hung et al. (U.S. Publication No. 2023/0386945 A1; hereinafter Hung) in view of Venkateshwaran et al. (U.S. Patent No. 6,339,254 B1; hereinafter Venkateshwaran)
With respect to claim 1, Hung discloses a semiconductor package comprising: a redistribution substrate [900] including a redistribution structure [920]; a sub-package [703] disposed on the redistribution substrate; a semiconductor chip [701] disposed on the redistribution substrate, wherein the semiconductor chip is positioned side-by-side with the sub-package; and an encapsulant [910/295], wherein the encapsulant encapsulates the sub-package, the semiconductor chip (see Figure 15A) Hun fails to disclose a heat dissipation structure disposed on the redistribution substrate and surrounding the sub-package and the semiconductor chip, but does disclose an underfill structure [950] comprising any known underfill material (See ¶[0050]) that surrounds the sub-package and the semiconductor chip and is encapsulated by [910] (See Figure 15A). In the same field of endeavor, Venkateshwaran teaches thermally conductive underfill material for heat dissipation (see Column 4, lines 44-64). Utilizing a thermally conductive underfill material as a heat dissipation structure surrounding the sub-package and the semiconductor chip as taught by Venkateshwaran allows for localized heat from circuits to be spread and conductive away from the source (see Column 4, lines 44-64). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention
With respect to claim 8, the combination of Hung and Venkateshwaran discloses wherein the sub-package includes a memory package (see Hung ¶[0044]).
Claim(s) 2-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hung in view of Venkateshwaran as applied to claim 1 above, and further in view of Lee et al. (U.S. Publication No. 2020/0168522 A1; hereinafter Lee)
With respect to claim 2, the combination of Hung and Venkateshwaran fails to disclose wherein the heat dissipation structure is formed from a material including crystalline silicon.
In the same field of endeavor, Lee teaches a heat dissipation structure [131] is formed from a material including crystalline silicon (See ¶[0050] and Figure 2A). Implementation of crystalline silicon within heat dissipation structures of the combination of Hung and Venkateshwaran allows for high thermal conductivity with less expense (See ¶[0050]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 3, the combination of Hung, Venkateshwaran, and Lee wherein an upper surface of the heat dissipation structure layer has a [100] crystal plane, however it has been held that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention to determine the optimal crystal plane for optimal heat dissipation within the structure.
With respect to claim 4, the combination of Hung, Venkateshwaran, and Lee discloses wherein the heat dissipation structure comprises a plurality of through openings (See Hung Figure 15A and Venkateshwaran Figure 4; through openings allow for contact bumps to connect to redistribution structure).
With respect to claim 5, the combination of Hung, Venkateshwaran, and Lee discloses wherein the sub-package is electrically connected to the redistribution structure via a first through opening of the plurality of through openings, and the semiconductor chip is electrically connected to the redistribution structure via a second through opening of the plurality of through openings (See Hung Figure 15A and Venkateshwaran Figure 4; through openings allow for contact bumps to connect to redistribution structure).
With respect to claim 6, the combination of Hung, Venkateshwaran, and Lee discloses wherein an inner sidewall of each of the plurality of through openings has a predetermined slope from a top of the through opening to a bottom of the through opening (See Hung Figure 15A, slope is predetermined by shape of bump structures).
With respect to claim 7, the combination of Hung, Venkateshwaran, and Lee fails to explicitly disclose wherein an inner sidewall of each of the plurality of through openings has a [111] crystal plane however it has been held that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention to determine the optimal crystal plane for optimal heat dissipation within the structure.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hung in view of Venkateshwaran as applied to claim 1 above, and further in view of Wang et al. (U.S. Publication No. 2022/0122896 A1; hereinafter Wang).
With respect to claim 9, the combination of Hung and Venkateshwaran fails to disclose wherein a thermal expansion coefficient of the heat dissipation structure is less than a thermal expansion coefficient of the encapsulant. In the same field of endeavor, Wang teaches wherein a thermal expansion coefficient of the heat dissipation structure is less than a thermal expansion coefficient of the encapsulant (see ¶[0049]). Implementation of a coefficient of thermal expansion for the heat dissipation structure that is less than that of the encapsulant reduces stress applied to the substrate, thereby controlling warpage (see ¶[0049]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hung in view of Venkateshwaran as applied to claim 1 above, and further in view of Yu et al. (U.S. Publication No. 2023/0352367 A1; hereianfter Yu)
With respect to claim 10, the combination of Hung and Venkateshwaran fails to disclose wherein a thermal conductivity of the heat dissipation structure is greater than a thermal conductivity of the encapsulant.
In the same field of endeavor, Yu teaches a thermal conductivity of the heat dissipation structure is greater than a thermal conductivity of the encapsulant (See ¶[0034]). Implementation of a heat dissipation structure with greater thermal conductivity than that of the encapsulant as taught by Yu facilitates efficient heat dissipation away from the source before the encapsulant can be affected by the increase in heat, causing warping and damage (see ¶[0034]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
Claim(s) 11 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hung in view of Nakasato et al. (U.S. Publication No. 2010/0264552 A1; hereinafter Nakasato).
With respect to claim 11, Hung discloses semiconductor package comprising: a redistribution substrate [900] including a redistribution structure [920]; a memory package [703] disposed on the redistribution substrate; a first connector [780] disposed between the redistribution substrate and the memory package; a system-on-chip (SOC) [701] disposed on the redistribution substrate and side-by-side with the memory package; a second connector [780] disposed between the redistribution substrate and the system-on-chip; an encapsulant [910/295], wherein the encapsulant encapsulates the memory package, the system-on-chip, and the heat dissipation structure; a connection member [290] that connects the redistribution substrate to a component external [200] to the semiconductor package.
Hung fails to disclose a heat dissipation structure disposed on the redistribution substrate and between the memory package and the system-on-chip; and an adhesive layer connecting the redistribution substrate and the heat dissipation structure, wherein the top of the heat dissipation structure is lower than the top of the memory package or the system-on-chip, but does disclose an underfill structure [950] comprising any known underfill material (See ¶[0050]) that surrounds the sub-package and the semiconductor chip and is encapsulated by [910] (See Figure 15A). In the same field of endeavor, Nakasato teaches a heat dissipation structure [29] disposed on the redistribution substrate and between the memory package and the system-on-chip (see ¶[0132]); and an adhesive layer [4] connecting the redistribution substrate and the heat dissipation structure, wherein the top of the heat dissipation structure is lower than the top of the memory package or the system-on-chip (Nakasato ¶0053-0054]). Implementation of Nakasato’s heat dissipation underfill and adhesive layer allows for improved heat dissipation away from active devices (See Nakasato ¶[0132]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 12, the combination of Hung and Nakasato discloses wherein a sidewall of the heat dissipation structure has a predetermined slope from a top of the through opening to a bottom of the through opening (See Hung Figure 15A, slope is predetermined by shape of bump structures and Nakasato Figure 1B).
Allowable Subject Matter
Claim 13 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
With respect to claim 13, none of the prior art teaches or suggests, alone or in combination, wherein a width of an upper surface of the heat dissipation structure is greater than a width of a lower surface of the heat dissipation structure.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. - Yu et al. (U.S. Publication No. 2021/0327866 A1) discloses heat dissipation structures but fails to disclose wherein a width of an upper surface of the heat dissipation structure is greater than a width of a lower surface of the heat dissipation structure.
Lin et al. (U.S. Patent No. 10,170,341 B1) discloses heat dissipation structures but fails to disclose wherein a width of an upper surface of the heat dissipation structure is greater than a width of a lower surface of the heat dissipation structure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONATHAN HAN whose telephone number is (571)270-7546. The examiner can normally be reached 9.00-5.00PM PST.
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/JONATHAN HAN/Primary Examiner, Art Unit 2818
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