DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim and Specification Status
The Examiner acknowledges the amendments to claims 1, 9 and 10 in the Applicant’s response dated 4 March 2026. The claim amendments have been addressed below.
The Examiner acknowledges the amendments to the title in the Applicant’s response dated 4 March 2026. The objection to the title as presented in the previous office action has therefore been withdrawn.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 5-6, 8 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hirotaka Otake et al. (US 2022/0165875 A1; hereinafter “Otake”).
Regarding Claim 1, Otake teaches a semiconductor device comprising:
a semiconductor layer including an electron transit layer (16, Fig. 38, para [0054] describes an electron transit layer 16) and an electron supply layer (18, Fig. 38, para [0054] describes an electron supply layer 18 wherein electron supply layer 18 and electron transit layer 16 comprise layers of a semiconductor layer);
a gate electrode (28, Fig. 38, para [0061] describes a gate electrode 28), a source electrode (32, Fig. 38, para [0061] describes a source electrode 32) and a drain electrode (34, Fig. 38, para [0061] describes a drain electrode 34), the gate electrode, the source electrode and the drain electrode being disposed on the semiconductor layer (28, 32 and 34, Fig. 38 depicts wherein the gate electrode 28, source electrode 32 and drain electrode 34 are disposed on their own respective portions of the semiconductor layer); and
a metal film connected to the gate electrode (30, Fig. 38, para [0077] describes a passivation layer 30 connected to the gate electrode 28 wherein the passivation layer can be a metal film such as aluminum oxynitride),
wherein the semiconductor layer includes an active region (810, Fig. 37, para [0227] describes an active region 810 portion of the semiconductor layer), and an inactive region surrounding the active region in plan view (812, Fig. 37, para [0227] describes an inactive region 812 portion of the semiconductor layer surrounding the active region 810 as shown in Fig. 37), the active region and the inactive region being disposed within a same semiconductor layer (810 and 812, Fig. 38 depicts wherein active region 810 comprises the same semiconductor layers 18 and 16 as the inactive region 812 as shown in Fig. 39),
wherein the gate electrode includes, in plan view, a first region overlapping the active region (FR, annotated Fig. 37 depicts a first region of the gate electrode 28 in the active region 810), and two second regions having the first region interposed therebetween, the two second regions both overlapping the inactive region (SR, annotated Fig. 37 depicts two second regions of the gate electrode 28 overlapping the inactive region 812 wherein the first region FR is interposed therebetween the second regions SR), and
wherein the metal film contacts the two second regions (30, Fig. 39, para [0230] describes wherein the metal film 30 contacts the gate electrodes 28 in the inactive region 812 as shown in Fig. 39 resulting in the metal film 30 contacting the two second regions SR).
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Regarding Claim 2, Otake teaches the semiconductor device as claimed in claim 1, further comprising: an insulating film supporting the metal film (24, Fig. 38, para [0070] describes a first passivation layer 24 comprised of an insulating material which can be seen as supporting the metal film 30 in Fig. 38 and Fig. 39).
Regarding Claim 5, Otake teaches the semiconductor device as claimed in claim 1, wherein in plan view, a dimension of each of the second regions in a direction in which the source electrode and the drain electrode (32 and 34, annotated Fig. 37 depicts wherein the source electrode 32 and drain electrode 34 are aligned in both an +X direction and +Y direction in the center region of the plan view) are aligned is 2 pm or more (SR and 22A, annotated Fig. 37, Fig. 38 and Fig. 39, para [0326] describes wherein a width of a first extension portion 22A as shown in Fig. 38 is 0.1 μm or more, resulting in a width of 100000 pm or more, wherein extension portion 22A comprises a width in the +X direction in which the source electrode 32 and drain electrode 34 are aligned wherein a portion of the gate electrode 28 in the second region SR fills in the width of the extension portion 22A in the second region SR as shown in Fig. 39 resulting in a width of the extension portion 22A being at least 0.1 μm in an +X direction which is more than 2 pm).
Regarding Claim 6, Otake teaches the semiconductor device as claimed in claim 1, wherein in plan view, in a direction in which the source electrode and the drain electrode are aligned (32 and 34, annotated Fig. 37 depicts wherein the source electrode 32 and drain electrode 34 are aligned in both an +X direction and +Y direction in the center region of the plan view), a dimension of the first region is smaller than a dimension of each of the second regions (FR and SR, annotated Fig. 37 depicts wherein the first region FR is smaller than the second region in an +X direction due to the presence of the source electrode 32 as shown in Fig. 38 and Fig. 39).
Regarding Claim 8, Otake teaches the semiconductor device as claimed in claim 1, wherein the semiconductor layer includes a plurality of the active regions (810, Fig. 37, para [0227] describes the active regions 810 comprising at least two as shown in Fig. 37), wherein the gate electrode includes the first region for each of the active regions (FR, annotated Fig. 37 depicts wherein the gate electrode 28 comprises the first region FR in both active regions 810), and wherein the second region is between two adjacent first regions (SR, annotated Fig. 37 depicts wherein the lower second region SR is between adjacent first regions FR of active regions 810).
Regarding Claim 10, Otake teaches a method of manufacturing a semiconductor device, the method comprising:
forming a semiconductor layer including an electron transit layer (16, Fig. 3, para [0054] describes forming an electron transit layer 16) and an electron supply layer (18, Fig. 3, para [0054] describes forming an electron supply layer 18 of a semiconductor layer);
forming a gate electrode (28, Fig. 7, para [0061] describes forming a gate electrode 28 on the semiconductor layers), a source electrode (32, Fig. 7, para [0061] describes forming a source electrode 32 on the semiconductor layers) and a drain electrode on the semiconductor layer (34, Fig. 7, para [0061] describes forming a drain electrode 34 on the semiconductor layers); and
forming a metal film connected to the gate electrode (30, Fig. 9, para [0061] describes forming a second passivation layer 30 connected to the gate electrode 28 wherein para [0077] describes wherein the passivation film may be a metal film such as aluminum oxynitride),
wherein the semiconductor layer includes an active region (810, Fig. 37, para [0227] describes an active region 810 portion of the semiconductor layer wherein para [0231] describes Fig. 37 may be applied to the nitride semiconductor apparatus formed in Fig. 2 through Fig. 11), and an inactive region surrounding the active region in plan view (812, Fig. 37, para [0227] describes an inactive region 812 portion of the semiconductor layer surrounding the active region 810 as shown in Fig. 37), the active region and the inactive region being disposed within a same semiconductor layer (810 and 812, Fig. 38 depicts wherein active region 810 comprises the same semiconductor layers 18 and 16 as the inactive region 812 as shown in Fig. 39 wherein Fig. 38 and Fig. 39 are an extension of Fig. 37 which may be applied to the nitride semiconductor apparatus formed in Fig. 2 through Fig. 11),
wherein the gate electrode includes, in plan view, a first region overlapping the active region (FR, annotated Fig. 37 depicts a first region of the gate electrode 28 in the active region 810), and two second regions having the first region interposed therebetween, the two second regions both overlapping the inactive region (SR, annotated Fig. 37 depicts two second regions of the gate electrode 28 overlapping the inactive region 812 wherein the first region FR is interposed therebetween the second regions SR), and
wherein the metal film contacts the two second regions (30, Fig. 39, para [0230] describes wherein the metal film 30 contacts the gate electrodes 28 in the inactive region 812 as shown in Fig. 39 resulting in the metal film 30 contacting the two second regions SR).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Hirotaka Otake et al. (US 2022/0165875 A1; hereinafter “Otake”) in view of Shuo-Yang Sun et al. (US 2018/0331130 A1; hereinafter “Sun”).
Regarding Claim 3, Otake discloses all the limitations of claim 2.
Otake teaches the semiconductor device as claimed in claim 2, wherein the insulating film includes a low permittivity film (24, Fig. 38, para [0070] describes a first passivation layer 24 comprised of an insulating material such as silicon dioxide resulting in a low permittivity film).
Otake fails to disclose wherein the insulating film includes a low permittivity film with a relative permittivity of 3.0 or less.
However, Sun teaches a semiconductor device wherein an insulating film includes a low permittivity film with a relative permittivity of 3.0 or less (140, Fig. 1, para [0046] describes a first dielectric layer that may be made of a PMMA resin wherein the dielectric constant is less than 4 and greater than 0, resulting in a low permittivity film with a relative permittivity of 3.0 or less).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Otake with Sun in order to disclose a PMMA resin film that has a permittivity of 3.0 or less to provide the well-known advantage of reducing unwanted electric field interactions in the underlying gate layers from which the insulating film surrounds.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Hirotaka Otake et al. (US 2022/0165875 A1; hereinafter “Otake”) in view of Shuo-Yang Sun et al. (US 2018/0331130 A1; hereinafter “Sun”) and in further view of Takahashi Takeshi (JP 2009-272433 using the PE2E English machine translation for rejection; hereinafter “Takeshi”).
Regarding Claim 4, the combination of Otake and Sun discloses all the limitations of claim 3.
The combination of Otake and Sun fails to explicitly disclose the semiconductor device as claimed in claim 3, wherein a cavity exists between the gate electrode and the low permittivity film.
However, Takeshi teaches a similar semiconductor device wherein a cavity exists between the gate electrode and the low permittivity film (6, Fig. 21, page 3 of the PE2E machine translation describes forming a space 6 around the gate electrode 30 and between the gate electrode 30 and the low permittivity film 4).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Otake and Sun with Takeshi in order to disclose a semiconductor device comprising a cavity between a gate electrode and a low permittivity film in order to provide the advantage of enabling a complete seal around a closed space and creating an elution port that may be easily sealed with a high yield around the gate electrode (Takeshi, PE2E English machine translation page 3 and page 8).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Hirotaka Otake et al. (US 2022/0165875 A1; hereinafter “Otake”) in view of Tetsuzo Nagahisa et al. (US 2017/0352753 A1; hereinafter “Nagahisa”).
Regarding Claim 7, Otake discloses all the limitations of claim 1.
Otake fails to explicitly disclose the semiconductor device as claimed in claim 1, wherein electrical resistance of the metal film is lower than electrical resistance of the first region.
However, Nagahisa teaches a similar semiconductor device, wherein electrical resistance of the metal film is lower than electrical resistance of the first region (14c and 14d, Fig. 11, para [0101] and para [0102] describe conductive layers 14c and 14d which make it possible to alleviate the concentration of an electric field on the gate electrode 7 which comprises a first region in an active region, wherein in order to have an electric field you have to have a potential difference between two sides of an element which only occurs if there is a resistance causing a potential difference that prevents voltage equilibrium, therefore a conductive layer such as found in Nagahisa would have a higher electrical conductivity than a first region of a gate electrode if it alleviates the concentration of an electric field on the gate electrode).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Otake with Nagahisa in order to disclose wherein a metal film has a lower electrical resistance than a first region of a gate electrode in order to provide the advantage of making it possible to suppress a collapse and improve breakdown voltage in the device (Nagahisa, para [0102]).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Hirotaka Otake et al. (US 2022/0165875 A1; hereinafter “Otake”) in view of the following arguments:
Regarding Claim 9, Otake discloses all the limitations of claim 1.
In the embodiment used to disclose all the limitations of claim 1, Takeshi fails to teach the semiconductor device as claimed in claim 1, further comprising: a passivation film covering the semiconductor layer and having a gate opening, wherein the gate electrode makes Schottky contact with the semiconductor layer through the gate opening, wherein the gate electrode includes: a first surface that is in contact with an upper surface of the passivation film at a position closer to the source electrode than is the gate opening, and a second surface that is in contact with the upper surface of the passivation film at a position closer to the drain electrode than is the gate opening, and wherein in plan view, an end of the second surface closer to the drain electrode is farther from the gate opening than an end of the first surface closer to the source electrode.
However, Otake teaches in a similar embodiment of their invention, wherein para [0236] describes said embodiment may be applied to the same embodiment as found in Fig. 37 used to teach the limitations of claim 1, a similar semiconductor device, further comprising:
a passivation film covering the semiconductor layer and having a gate opening (502, Fig. 17, para [0167] describes a third passivation layer 502 which can be seen covering the semiconductor layers 16 and 18 and having a gate opening 502A), and
wherein the gate electrode makes Schottky contact with the semiconductor layer through the gate opening (28 and 26, Fig. 17, para [0076] describes wherein gate electrode 28 and gate layer 26 of the semiconductor layers form a Schottky junction wherein the Schottky junction would occur through the gate opening 502A),
wherein the gate electrode (28, Fig. 17, para [0061] describes a gate electrode 28) includes:
a first surface that is in contact with an upper surface of the passivation film at a position closer to the source electrode than is the gate opening (FSF, annotated Fig. 17 depicts a first surface FSF of gate electrode 28 that is in contact with an upper surface of the passivation film 502 closer to source electrode 32A than the gate opening 502A as shown in annotated Fig. 17 below), and
a second surface that is in contact with the upper surface of the passivation film at a position closer to the drain electrode than is the gate opening (SFS, annotated Fig. 17 depicts a second surface SSF of gate electrode 28 that is in contact with an upper surface of the passivation film 502 closer to drain electrode 34 than the gate opening 502A as shown in annotated Fig. 17 below, and
wherein in plan view, an end of the second surface closer to the drain electrode is farther from the gate opening than an end of the first surface closer to the source electrode (annotated Fig. 17 depicts wherein end portion of passivation film comprising second surface SSF is farther from the gate opening 502A than an end portion of passivation film comprising first surface FSF as shown in annotated Fig. 17 below).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Takeshi with Otake in order to disclose a passivation film having a first surface and second surface of a gate electrode in contact with an upper surface of a passivation film wherein an end portion of a second surface is farther away from a gate opening than an end portion of the first surface to provide the advantage of reducing the process damage of the underlying semiconductor layers (Otake, para [0183]).
Response to Arguments
Applicant's arguments filed 4 March 2026 have been fully considered but they are not persuasive. The Applicant argues on page 8, lines 13-15, that the prior art of record, either alone or in combination, fail to disclose or suggest the amended feature “the active region and the inactive region being disposed within a same semiconductor layer”. The Examiner respectfully disagrees. As indicated in the U.S.C 102(a)(1) rejection above, the prior art of record, Otake, discloses the active region and the inactive region being disposed within a same semiconductor layer (810 and 812, Fig. 38 depicts wherein active region 810 comprises the same semiconductor layers 18 and 16 as the inactive region 812 as shown in Fig. 39). Therefore, Otake teaches the amended language of claim 1 and therefore the amendment is not deemed to patentably distinguish the Applicant’s claimed device from the device of Otake.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER M MILLER whose telephone number is (571)272-6051. The examiner can normally be reached Monday - Friday 8:00 am - 4:00 pm.
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/ALEXANDER MICHAEL MILLER/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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