Attorney’s Docket Number: QC2301821
Filing Date: 09/18/2023
Claimed Foreign Priority Date: none
Applicants: Sun et al.
Examiner: Younes Boulghassoul
DETAILED ACTION
This Office action responds to the Election filed on 03/05/2026.
Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election without traverse of Group Invention I (directed to a semiconductor structure), in the reply filed on 03/05/2026, is acknowledged. Applicant indicated that claims 1-10 and 21-31 read on the elected Group Invention. The examiner agrees. Accordingly, pending in this application are claims 1-31, with claims 11-20 standing withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group Invention, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 10, 21-24, and 30-31 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Glass et al. (US2019/0221649).
Regarding Claim 1, Glass (see, e.g., Fig. 7M and Par. [0060]-[0071]) shows all aspects of the instant invention, including a semiconductor device structure, comprising:
- a gate stack extending along a first direction in a front portion of the semiconductor structure (see, e.g., Figs. 7F-7G: gate stack extending along direction X), the gate stack including a first gate structure (e.g., gate structure associated with later-formed n-MOS FinFET)
- a first channel structure disposed through the first gate structure and extending along a second direction from a first side of the first gate structure to a second side of the first gate structure (see, e.g., Figs. 7F-7G: channel portion of fin associated with later-formed n-MOS FinFET, covered by gate stack and extending in direction Z)
- a first source/drain (S/D) structure adjacent the first gate structure and electrically coupled to the first channel structure (see, e.g., Figs. 7G,7M: n-MOS S/D)
- a backside dielectric layer disposed in a back portion of the semiconductor structure opposing the front portion (see, e.g., Figs. 7J,7M: backside insulator)
- a backside conductive structure in contact with the first S/D structure and disposed at least partially in the back portion of the semiconductor structure and through the backside dielectric layer (see, e.g., Fig. 7M: “long” backside S/D contact)
- wherein the backside conductive structure extends along the first direction and has a length in the first direction greater than a width of the first channel structure in the first direction (see, e.g., Figs. 7J,7M: “long” backside S/D contact extends along X and fills a backside contact trench having a length greater than fin/channel width of n-MOS FinFET along X)
Regarding Claim 2, Glass (see, e.g., Fig. 7M and Par. [0060]-[0071]) shows:
- a second channel structure disposed through a second gate structure included in the gate stack and extending along the second direction from a third side of the second gate structure to a fourth side of the second gate structure (see, e.g., Figs. 7F-7G: channel portion of fin associated with later-formed p-MOS FinFET, covered by gate stack and extending in direction Z), and the second gate structure being offset from the first gate structure in the first direction (see, e.g., Figs. 7G,7H: gate of later-formed p-MOS FinFET is offset from gate of later-formed n-MOS FinFET in direction X)
- a second S/D structure adjacent the second gate structure and electrically coupled to the second channel structure (see, e.g., Figs. 7G,7M: p-MOS S/D)
- wherein the first S/D structure has a first doping type, and the second S/D structure has a second doping type different from the first doping type (e.g., n doping of n-MOS S/D vs. p doping of p-MOS S/D)
Regarding Claim 3, Glass (see, e.g., Fig. 7M) shows that the backside conductive structure (e.g., “long” backside S/D contact) extends along the first direction at least from the first S/D structure (e.g., n-MOS S/D) to a middle point between the first S/D structure and the second S/D structure (e.g., p-MOS S/D).
Regarding Claim 4, Glass (see, e.g., Fig. 7M) shows that the backside conductive structure (e.g., “long” backside S/D contact) extends along the first direction at least from the first S/D structure (e.g., n-MOS S/D) to the second S/D structure (e.g., p-MOS S/D) and is in contact with the second S/D structure.
Regarding Claim 10, Glass (see, e.g., Fig. 7M and Par. [0071],[0057]) shows that the backside conductive structure (e.g., “long” backside S/D contact) comprises tungsten, cobalt, molybdenum, ruthenium, or a combination thereof (e.g., tungsten).
Regarding Claim 21, Glass (see, e.g., Fig. 8 and Par. [0072]-[0078]) shows all aspects of the instant invention, including an electronic device (e.g., computing system 1000), comprising:
- an integrated circuit device (e.g., processor 1004) including a semiconductor structure (see, e.g., Par. [0076]: 1004 includes structures or devices formed using the disclosed techniques), and the semiconductor structure comprising all the limiting claimed features (see, e.g., Fig. 7M and Par. [0060]-[0071]). Also, see comments stated above in Par. 5 with regards to the semiconductor structure of Claim 1, which are considered repeated here.
Regarding Claim 22, see comments stated above in Par. 6 with regards to Claim 2, which are considered repeated here.
Regarding Claim 23, see comments stated above in Par. 7 with regards to Claim 3, which are considered repeated here.
Regarding Claim 24, see comments stated above in Par. 8 with regards to Claim 4, which are considered repeated here.
Regarding Claim 30, see comments stated above in Par. 9 with regards to Claim 10, which are considered repeated here.
Regarding Claim 31, Glass (see, e.g., Fig. 8 and Par. [0072]-[0078]) shows that the electronic device (e.g., 1000) comprises a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, or a device in an automotive vehicle.
Claims 1-2, 5-6, 9-10, 21-22, 25-26, 29, and 30 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Liaw (US2023/0378190).
Regarding Claim 1, Liaw (see, e.g., Figs. 3, 5B, and 6D) shows all aspects of the instant invention, including a semiconductor device structure (e.g., inverter logic cell 420), comprising:
- a gate stack extending along a first direction in a front portion of the semiconductor structure (e.g., gate 115c extending along direction Y), the gate stack including a first gate structure (e.g., gate structure 110,112 associated with N-type transistor N3)
- a first channel structure disposed through the first gate structure and extending along a second direction from a first side of the first gate structure to a second side of the first gate structure (e.g., channel nanostructures 120, surrounded by 115c and extending in direction X)
- a first source/drain (S/D) structure adjacent the first gate structure and electrically coupled to the first channel structure (e.g., source/drain feature 118 associated with N3)
- a backside dielectric layer disposed in a back portion of the semiconductor structure opposing the front portion (e.g., back-side dielectric layer 305)
- a backside conductive structure in contact with the first S/D structure and disposed at least partially in the back portion of the semiconductor structure and through the backside dielectric layer (e.g., source/drain backside contact 303d)
- wherein the backside conductive structure extends along the first direction and has a length in the first direction greater than a width of the first channel structure in the first direction (see, e.g., Fig. 5B: 303d extends along Y and has a length greater than a width of active 105a/channel 120 along Y)
Regarding Claim 2, Liaw (see, e.g., Figs. 3, 5B, and 6D) shows:
- a second channel structure disposed through a second gate structure included in the gate stack and extending along the second direction from a third side of the second gate structure to a fourth side of the second gate structure (e.g., channel nanostructures 120 disposed through gate structure 110,112 associated with P-type transistor P3, surrounded by 115c and extending in direction X), and the second gate structure being offset from the first gate structure in the first direction (e.g., Figs. P3 and N3 are offset in direction Y)
- a second S/D structure adjacent the second gate structure and electrically coupled to the second channel structure (e.g., source/drain feature 118 associated with P3)
- wherein the first S/D structure has a first doping type, and the second S/D structure has a second doping type different from the first doping type (see, e.g., Par. [0027]: standard cell INV 420 includes a PMOS transistor P3 and an NMOS transistor N3, thus implicitly discloses that S/D 118 of N3 is n-doped while S/D 118 of P3 is p-doped).
Regarding Claim 5, Liaw (see, e.g., Figs. 3 and 6D, and Par. [0032]-[0033]) shows that:
- the first channel structure comprises one or more channel members (e.g., stack of channel nanostructures 120 associated with N3)
- the first gate structure (e.g., gate structure 110,112 associated with N3) comprises:
a gate electrode structure (e.g., gate electrode 110)
one or more gate dielectric structures (e.g., gate dielectric layer 112) between the gate electrode structure and the respective one or more channel members.
Regarding Claim 6, Liaw (see, e.g., Figs. 3 and 6D, AND Par. [0032]) shows that the one or more channel members (e.g., 120) comprise a plurality of nanowires or nanosheets.
Regarding Claim 9, Liaw (see, e.g., Figs. 5B and 6D) shows:
- a metallization structure disposed in the back portion of the semiconductor structure (e.g., metal line 320a), and under and coupled to the backside conductive structure (e.g., 303d) through a backside via (e.g., via 315d)
- wherein the backside via (e.g., 315d) is offset from and non-overlapping with the first channel structure (e.g., 120s) in the first direction (e.g., Y).
Regarding Claim 10, Liaw (see, e.g., Par. [0083]) shows that the backside conductive structure (e.g., 303d) comprises tungsten, cobalt, molybdenum, ruthenium, or a combination thereof.
Regarding Claim 21, Liaw (see, e.g., Figs. 1A-B, 2A-B, and 5A-B; and Par. [0003], [0021], [0024]) shows all aspects of the instant invention, including an electronic device (e.g., electronic device including memory and/or core devices), comprising:
- an integrated circuit device (e.g., semiconductor device 400) including a semiconductor structure (e.g., inverter logic cell 420), and the semiconductor structure comprising all the limiting claimed features (see, e.g., Figs. 3, 5B, and 6D). Also, see comments stated above in Par. 17 with regards to the semiconductor structure of Claim 1, which are considered repeated here.
Regarding Claim 22, see comments stated above in Par. 18 with regards to Claim 2, which are considered repeated here.
Regarding Claim 25, see comments stated above in Par. 19 with regards to Claim 5, which are considered repeated here.
Regarding Claim 26, see comments stated above in Par. 20 with regards to Claim 6, which are considered repeated here.
Regarding Claim 29, see comments stated above in Par. 21 with regards to Claim 9, which are considered repeated here.
Regarding Claim 30, see comments stated above in Par. 22 with regards to Claim 10, which are considered repeated here.
Claims 1, 5-8, 10, 21, 25-28, and 30 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chiang et al. (US2021/0305252).
Regarding Claim 1, Chiang (see, e.g., Figs. 18-20) shows all aspects of the instant invention, including a semiconductor device structure, comprising:
- a gate stack extending along a first direction in a front portion of the semiconductor structure (see, e.g., Fig. 18A-B: one of gate stacks 240’ extending along direction Y), the gate stack including a first gate structure (e.g., gate structure comprising gate dielectric layer 349 and the gate electrode 350)
- a first channel structure disposed through the first gate structure and extending along a second direction from a first side of the first gate structure to a second side of the first gate structure (see, e.g., Fig. 18B: e.g., stack of channels 272 surrounded by 240’ and extending in direction X)
- a first source/drain (S/D) structure adjacent the first gate structure and electrically coupled to the first channel structure (see, e.g., Fig. 18B: “middle” S/D feature 260)
- a backside dielectric layer disposed in a back portion of the semiconductor structure opposing the front portion (see, e.g., Fig. 18B: dielectric layer 378)
- a backside conductive structure in contact with the first S/D structure and disposed at least partially in the back portion of the semiconductor structure and through the backside dielectric layer (see, e.g., Figs. 18B and 20A: backside source contact feature 384)
- wherein the backside conductive structure extends along the first direction and has a length in the first direction greater than a width of the first channel structure in the first direction (see, e.g., Figs. 18C and 20A: backside source contact feature 384 extends along Y and has a length along Y greater than a width of channel 272 along Y).
Regarding Claim 5, Chiang (see, e.g., Figs. 18B-C) shows that:
- the first channel structure comprises one or more channel members (e.g., stack of channels 272)
- the first gate structure comprises:
a gate electrode structure (e.g., gate electrode 350)
one or more gate dielectric structures (e.g., gate dielectric layer 349) between the gate electrode structure and the respective one or more channel members.
Regarding Claim 6, Chiang (see, e.g., Figs. 18-20 and Par. [0021]) shows that the one or more channel members (e.g., 272) comprise a plurality of nanowires or nanosheets (e.g., for implementing nanosheet or nanowire FETs).
Regarding Claim 7, Chiang (see, e.g., Figs. 17B and 18B) shows that an upper portion of the backside conductive structure (e.g., “mushroom-shaped” portion of 384) is in contact with a bottom inner spacer of the first gate structure and a bottom inner spacer of another gate structure that is offset from the first gate structure in the second direction (e.g., inner spacers 255 flanking 384 in the X direction).
Regarding Claim 8, Chiang (see, e.g., Figs. 17B and 18B) shows that a first width of the upper portion of the backside conductive structure in the second direction (e.g., width of “mushroom-shaped” portion of 384 along X) is greater than a second width of a lower portion of the backside conductive structure in the second direction (e.g., width of “straight” portion of 384 along X).
Regarding Claim 10, Chiang (see, e.g., Par. [0073]) shows that the backside conductive structure (e.g., 384 comprising barrier 386 and fill 388) comprises tungsten, cobalt, molybdenum, ruthenium, or a combination thereof.
Regarding Claim 21, Chiang (see, e.g., Par [0021]) shows all aspects of the instant invention, including an electronic device (e.g., IC chip or system on chip (SoC)), comprising:
- an integrated circuit device (e.g., device 200) including a semiconductor structure, and the semiconductor structure comprising all the limiting claimed features (see, e.g., Figs. 18-20). Also, see comments stated above in Par. 30 with regards to the semiconductor structure of Claim 1, which are considered repeated here.
Regarding Claim 25, see comments stated above in Par. 31 with regards to Claim 5, which are considered repeated here.
Regarding Claim 26, see comments stated above in Par. 32 with regards to Claim 6, which are considered repeated here.
Regarding Claim 27, see comments stated above in Par. 33 with regards to Claim 7, which are considered repeated here.
Regarding Claim 28, see comments stated above in Par. 34 with regards to Claim 8, which are considered repeated here.
Regarding Claim 30, see comments stated above in Par. 35 with regards to Claim 10, which are considered repeated here.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional references cited disclose GAA-based semiconductor structures with backside S/D contacts, and having features similar to the instant inventions.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Younes Boulghassoul at (571) 270-5514. The examiner can normally be reached on Monday-Friday 9am-6pm EST (Eastern Standard Time), or by e-mail via younes.boulghassoul@uspto.gov. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached at (571) 272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YOUNES BOULGHASSOUL/Primary Examiner, Art Unit 2814
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