DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-10 and 21-30 in the reply filed on 03/13/2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 4, 6-10, 21-22, 24, and 26-31 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang et al. (US 11658119 B2, hereinafter Huang)
With regards to claim 1, Huang discloses a semiconductor structure, (FIGS. 11A-14) comprising:
a gate stack (at least gate 255) extending along a first direction in a front portion of the semiconductor structure, the gate stack including a first gate structure (right gate 255) and a second gate structure (left gate 255) offset from each other in the first direction; (See FIG. 11A-14)
a first source/drain (S/D) structure (source/drain 260P) adjacent the first gate structure;
a second S/D structure (source/drain 260N) adjacent the second gate structure, the second S/D structure being offset from the first S/D structure in a second direction; (See FIG. 11A-14)
a first backside conductive structure (at least conductive structure 282 on 260P) in contact with the first S/D structure and disposed at least partially in a back portion of the semiconductor structure opposing the front portion; (see FIGS. 1 and 2A)
a second backside conductive structure (at least conductive structure 282 on 260N) in contact with the second S/D structure and disposed at least partially in the back portion of the semiconductor structure; and
a third backside conductive structure (interconnect 406) disposed in the back portion of the semiconductor structure, the third backside conductive structure extending along the second direction and in contact with the first backside conductive structure and the second backside conductive structure. (see FIGS. 11A-14, showing the interconnect in the second direction)
With regards to claim 2, Huang discloses the semiconductor structure of claim 1, wherein:
the first backside conductive structure and the second backside conductive structure are disposed within a first backside metallization layer under the first S/D structure and the second S/D structure, and the third backside conductive structure is disposed within a second backside metallization layer under the first backside metallization layer. (See FIGS. 11-14)
With regards to claim 4, Huang discloses the semiconductor structure of claim 1, wherein:
the first backside conductive structure and the second backside conductive structure are disposed within a first backside metallization layer under the first S/D structure and the second S/D structure, and the third backside conductive structure is disposed within a lower portion of the first backside metallization layer. (see FIG. 14)
With regards to claim 6, Huang discloses the semiconductor structure of claim 1, further comprising:
a dielectric structure (at least isolation structure 230/408) under a connecting portion of the gate stack between the first gate structure and the second gate structure, wherein:
the third backside conductive structure is disposed at least partially under the connecting portion of the gate stack, the dielectric structure being configured to electrically isolate the third backside conductive structure from a bottom gate electrode portion of the connecting portion of the gate stack. (see FIG. 14)
With regards to claim 7, Huang discloses the semiconductor structure of claim 6, wherein:
the dielectric structure is in contact with the bottom gate electrode portion of the connecting portion of the gate stack. (See FIGS. 11A-14)
With regards to claim 8, Huang discloses the semiconductor structure of claim 7, wherein:
at least a portion of the third backside conductive structure is above a lower surface of the gate stack and extends along an inner spacer of the connecting portion of the gate stack. (See FIG. 14)
With regards to claim 9, Huang discloses the semiconductor structure of claim 6, wherein:
an entirety of the third backside conductive structure is below the connecting portion of the gate stack. (See FIG. 14)
With regards to claim 10, Huang discloses the semiconductor structure of claim 6, wherein:
the dielectric structure comprises an etch stop layer (dielectric 269) under the connecting portion of the gate stack. (See FIGS. 11A-14)
With regards to claim 21, Huang discloses an electronic device, (FIGS. 11A-14) comprising:
an integrated circuit device (integrated circuit having semiconductor device 200) including a semiconductor structure, and the semiconductor structure comprising:
a gate stack (at least gate 255) extending along a first direction in a front portion of the semiconductor structure, the gate stack including a first gate structure (right gate 255) and a second gate structure (left gate 255) offset from each other in the first direction; (See FIG. 11A-14)
a first source/drain (S/D) structure (source/drain 260P) adjacent the first gate structure;
a second S/D structure (source/drain 260N) adjacent the second gate structure, the second S/D structure being offset from the first S/D structure in a second direction; (See FIG. 11A-14)
a first backside conductive structure (at least conductive structure 282 on 260P) in contact with the first S/D structure and disposed at least partially in a back portion of the semiconductor structure opposing the front portion; (see FIGS. 1 and 2A)
a second backside conductive structure (at least conductive structure 282 on 260N) in contact with the second S/D structure and disposed at least partially in the back portion of the semiconductor structure; and
a third backside conductive structure (interconnect 406) disposed in the back portion of the semiconductor structure, the third backside conductive structure extending along the second direction and in contact with the first backside conductive structure and the second backside conductive structure. (see FIGS. 11A-14, showing the interconnect in the second direction)
With regards to claim 22, Huang discloses the electronic device of claim 21, wherein:
the first backside conductive structure and the second backside conductive structure are disposed within a first backside metallization layer under the first S/D structure and the second S/D structure, and the third backside conductive structure is disposed within a second backside metallization layer under the first backside metallization layer. (See FIGS. 11A-14)
With regards to claim 24, Huang discloses the electronic device of claim 21, wherein:
the first backside conductive structure and the second backside conductive structure are disposed within a first backside metallization layer under the first S/D structure and the second S/D structure, and the third backside conductive structure is disposed within a lower portion of the first backside metallization layer. (see FIG. 14)
With regards to claim 26, Huang discloses the electronic device of claim 21, wherein the semiconductor structure further comprises:
a dielectric structure (at least isolation structure 230/408) under a connecting portion of the gate stack between the first gate structure and the second gate structure,
wherein the third backside conductive structure is disposed at least partially under the connecting portion of the gate stack, the dielectric structure being configured to electrically isolate the third backside conductive structure from a bottom gate electrode portion of the connecting portion of the gate stack. (see FIG. 14)
With regards to claim 27, Huang discloses the electronic device of claim 26, wherein:
the dielectric structure is in contact with the bottom gate electrode portion of the connecting portion of the gate stack. (See FIG. 14)
With regards to claim 28, Huang discloses the electronic device of claim 27, wherein:
at least a portion of the third backside conductive structure is above a lower surface of the gate stack and extends along an inner spacer of the connecting portion of the gate stack. (See FIG. 14)
With regards to claim 29, Huang discloses the electronic device of claim 26, wherein:
an entirety of the third backside conductive structure is below the connecting portion of the gate stack. (See FIG. 14)
With regards to claim 30, Huang discloses the electronic device of claim 26, wherein:
the dielectric structure comprises an etch stop layer (dielectric 269) under the connecting portion of the gate stack. (See FIG. 14)
With regards to claim 31, Huang discloses the electronic device of claim 21, wherein the electronic device comprises a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, (integrated circuit, i.e. a computer, see background) a wearable device, a laptop computer, a server, an internet of things (IoT) device, or a device in an automotive vehicle.
Allowable Subject Matter
Claims 3, 5, 23, and 25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 20230238441 A1 – interconnect structure on backside on S/D
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN M Page whose telephone number is (571)272-3249. The examiner can normally be reached M-F: 10:00AM-6:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8548. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STEVEN M PAGE/Primary Patent Examiner, Art Unit 2812
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