Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-15 in the reply filed on 2/27/2026 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 9/18/2023 and 2/7/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1- 5 and 13-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wei US 2023/0067354.
Re claim 1, Wei teaches a gate-tie-down (GTD) cell (fig1A and 1B), comprising:
first (116a, fig1A and 1B, [19]) and second edge gates (116b, fig1A and 1B, [19]) extending in a first direction (along 110 direction in fig1B around nanoribbons 112, fig1A and 1B), the first and second edge gates defining boundaries of the GTD cell (part of 116a and 116b directly over 118a/b define boundaries of the GTD cell, fig1A and 1B);
a channel ribbon (112, fig1A/B, [23]) extending in a second direction (along line between 118a and 118b, fig1A/B) different from the first direction from the first edge gate to the second edge gate (112 of each layer extend from 116a side to 116b side, fig1A), the channel ribbon (112, fig1A/B, [23]) being formed at least partially within the first and second edge gates (116a and 116b, fig1A and 1B, [19]);
a backside power (BSP) rail (122a/b in 106, fig1A, [29]) extending in the second direction (along line between 118a and 118b, fig1A/B), the BSP rail (122a/b in 106, fig1A, [29]) being formed below the first and second edge gates (116a and 116b, fig1A and 1B, [19]) and below the channel ribbon (112, fig1A/B, [23]); and
a BSP trench (118a and 118b, fig1A/1B, [25]) extending in the second direction (along line between 118a and 118b, fig1A/B), the BSP trench (118a and 118b, fig1A/1B, [25]) being formed on the BSP rail (122a/b in 106, fig1A, [29]), the BSP trench (118a and 118b, fig1A/1B, [25]) being conductive and electrically coupled with the BSP rail (122a/b in 106, fig1A, [29]) and with the first and second edge gates (116a and 116b, fig1A and 1B, [19]),
wherein a first edge portion (part of 112 adjacent to 118a, fig1A) of the channel ribbon within the first edge gate (116a, fig1A and 1B, [19]) is configured to prevent a first channel (112 in 116a, fig1A) being formed therein when a turn-off voltage is applied to the first edge gate (fig1A and 1B, [10]),
wherein a second edge portion (part of 112 adjacent to 118b, fig1A) of the channel ribbon within the second edge gate (116b, fig1A and 1B, [19]) is configured to prevent a second channel (112 in 116b, fig1A) being formed therein when the turn-off voltage is applied to the second edge gate (fig1A and 1B, [10]), and
wherein the BSP rail (122a/b in 106, fig1A, [29]) is configured to apply the turn-off voltage to the first and second edge gates through the BSP trench (118a and 118b, fig1A/1B, [10, 25]).
Re claim 2, Wei teaches the GTD cell of claim 1, wherein the first (along 110 direction in fig1B around nanoribbons 112, fig1A and 1B) and second (along line between 118a and 118b, fig1A/B) directions are orthogonal to each other.
Re claim 3, Wei teaches the GTD cell of claim 1, wherein the BSP trench (118a and 118b, fig1A/1B, [25]) is in direct contact with the BSP rail (122a/b in 106, fig1A, [29]), the first edge gate, the second edge gate, or any combination thereof.
Re claim 4, Wei teaches the GTD cell of claim 1, wherein the first edge gate (116a, fig1A and 1B, [19]) at least partially surrounds the first edge portion (part of 112 adjacent to 118a, fig1A), or wherein the second edge gate (116b, fig1A and 1B, [19]) at least partially surrounds the second edge portion (part of 112 adjacent to 118b, fig1A), or both.
Re claim 5, Wei teaches the GTD cell of claim 1, wherein when the turn-off voltage is applied ([10]), the first edge portion (part of 112 adjacent to 118a, fig1A) electrically isolates a first inside portion from a first outside portion (fig1A and 1B, [10]), or the second edge portion (part of 112 adjacent to 118b, fig1A) electrically isolates a second inside portion from a second outside portion (fig1A and 1B, [10]), the first inside and outside portions being portions of the channel ribbon on sides of the first edge portion respectively within the GTD cell and outside the GTD cell, and the second inside and outside portions being portions of the channel ribbon on sides of the second edge portion respectively within the GTD cell and outside the GTD cell (fig1A and 1B, [10]).
Re claim 13, Wei teaches the GTD cell of claim 1, wherein the BSP trench (118a and 118b, fig1A/1B, [25]) is formed from any one or more of copper (Cu) ([25]), cobalt (Co) ([25]), molybdenum (Mo) ([25]), tungsten (W) ([25]), ruthenium (Ru) ([25]), titanium aluminide (TiAl), and titanium nitride (TiN).
Re claim 14, Wei teaches the GTD cell of claim 1, wherein the cell is a fin-shaped field effect transistor (FinFET) cell or a gate all around (GAA) cell (GAA, fig1A).
Re claim 15, Wei teaches the GTD cell of claim 1, wherein the GTD cell is incorporated into an apparatus selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of things (IoT) device, a laptop computer, a server, and a device in an automotive vehicle (fig5, [74, 78]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6-12 are rejected under 35 U.S.C. 103 as being unpatentable over Wei US 2023/0067354 and Park et al. US 2023/0027769.
Re claim 6, Wei teaches the GTD cell of claim 1 with gate-tied down devices at cell boundaries and have other transistors having same structure within the cell ([10]).
Wei does not explicitly show the detail layout of the other transistors within the cell.
Park teaches an interior gate (AG2, AG3, fig1, [30]) extending in the first direction (Y, fig1), the interior gate being between the first and second edge gates (TG1 and TG2, fig1, [30]), wherein the channel ribbon (12, fig2A, [37]) is at least partially within the interior gate, and wherein an interior portion of the channel ribbon within the interior gate is configured to form an interior channel therein when a turn-on voltage is applied to the interior gate and configured to prevent the interior channel from being formed therein when the turn-off voltage is applied to the interior gate.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Wei and Park to add in the other transistors having same structure within the cell as in Park fig1. The motivation to do so is to improve integration of the device (Park, [62]).
Re claim 7, Wei modified above teaches the GTD cell of claim 6, wherein the interior gate is not electrically coupled to the BSP rail (Park, AG2 and AG3 between tie gate TG1 and TG2, fig1, [30]).
Re claim 8, Wei modified above teaches the GTD cell of claim 6, further comprising: a first source/drain (S/D) (S/D as 126a/b in Wei fig1B formed on side of active gates as in Park added between Wei 116a and 116b) formed between the first edge gate (Wei, 116a, fig1A and 1B, [19]) and the interior gate (active gates as in Park added between 116a and 116b of Wei in fig1A/B) above the backside dielectric, the channel ribbon being in electrical contact with the first S/D (Park, fig1); and a second S/D (S/D as 128a/b in Wei fig1B formed on side of active gates as in Park added between Wei 116a and 116b) formed between the second edge gate (Wei, 116b, fig1A and 1B, [19]) and the interior gate (active gates as in Park added between 116a and 116b of Wei in fig1A/B), the channel ribbon being in electrical contact with the second S/D (Park, fig1), wherein when the turn-on voltage is applied to the interior gate, the interior channel electrically couples the first S/D with the second S/D (Park, fig1).
Re claim 9, Wei modified above teaches the GTD cell of claim 8, further comprising: a first trench contact (Park, CA12/11, fig2B, [60]) formed on and electrically coupled with the first S/D (S/D as 126a/b in Wei fig1B formed on side of active gates as in Park added between Wei 116a and 116b); and a second trench contact (Park, CA22 and contact on SD25, fig1 and 2C, [78]) formed on and electrically coupled with the second S/D (S/D as 128a/b in Wei fig1B formed on side of active gates as in Park added between Wei 116a and 116b).
Re claim 10, Wei modified above teaches the GTD cell of claim 9, wherein one of the first and second trench contacts is electrically coupled with the BSP rail and other of the first and second trench contacts is not electrically coupled with the BSP rail (Park, only CA11/12 coupled with tie gate electrodes, fig1).
Re claim 11, Wei modified above teaches the GTD cell of claim 10, wherein the one of the first and second trench contacts is in direct contact with the BSP trench (Park, only CA11/12 direct contact VDD, fig1).
Re claim 12, Wei does not explicitly show the GTD cell of claim 9, wherein the BSP trench, the first trench contact, and the second trench contact are formed from same material.
Wei teaches contact 118a/b formed of tungsten ([25]), copper ([25]) or silver ([25]) in contact with the gate structure.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Wei and Park to form S/D contact and gate contact with the same metal material and process to simplify process and reduce contact resistance.
Conclusion
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/XIAOMING LIU/Examiner, Art Unit 2812
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