Prosecution Insights
Last updated: April 19, 2026
Application No. 18/469,493

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Non-Final OA §102§103
Filed
Sep 18, 2023
Examiner
MENZ, DOUGLAS M
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Mitsubishi Electric Corporation
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
2y 3m
To Grant
93%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allow Rate
670 granted / 760 resolved
+20.2% vs TC avg
Minimal +5% lift
Without
With
+4.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
30 currently pending
Career history
790
Total Applications
across all art units

Statute-Specific Performance

§101
1.8%
-38.2% vs TC avg
§103
36.0%
-4.0% vs TC avg
§102
53.2%
+13.2% vs TC avg
§112
2.3%
-37.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 760 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Species I of Group I, claims 1-5, in the reply filed on 12/18/25 is acknowledged. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 3 and 4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by JP H06-155513A (partial translation provided by Applicant and referenced as ‘513). Regarding claim 1, ‘513 discloses a method of manufacturing a semiconductor device in which an electrical circuit including a semiconductor chip (6, figs. 2-4) and a plurality of metal wires (8, figs. 2-4) electrically connected to the semiconductor chip is sealed with a sealing material (9, figs. 3-4 and paragraphs 0006-0008), comprising steps of: filling a cavity and at least a part of a sealing material storage part with the sealing material by injecting the sealing material from a first gate of a mold (fig. 3 and paragraphs 0006-0008), the mold including the cavity in which the electrical circuit is disposed, the first gate and a second gate provided to the cavity, and the sealing material storage part provided to an outer side of the cavity to be connected to the second gate (4, fig. 3 and paragraphs 0006-0008); and making the sealing material filling the sealing material storage part flow back to the cavity via the second gate (fig. 4 and paragraphs 0006-0008). Regarding claim 3, ‘513 further discloses wherein the second gate (4, figs. 3-4) is disposed near a metal wire (8, figs. 3-4) extending in a direction having a largest angle in a plurality of angles between a direction in which the sealing material is injected into the cavity from the first gate and a direction in which each of the plurality of metal wires extends in a plan view (figs. 3-4). Regarding claim 4, ‘513 further discloses wherein the sealing material is injected (port 3, fig. 3, vertical direction) from a direction perpendicular to the direction in which each of the plurality of metal wires extends (8, fig. 3, horizontal direction). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 2 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over JP H06-155513A (partial translation provided by Applicant and referenced as ‘513). Regarding claim 2, ‘513 discloses the method of manufacturing the semiconductor device according to claim 1, as mentioned above, and further discloses wherein the sealing material is resin (9, figs. 3-4 and paragraphs 0006-0008). ‘513 does not explicitly disclose hardening the sealing material after the sealing material flows back to the cavity via the second gate; and removing the sealing material which has been hardened and extends from the first gate or the second gate toward the outer side of the cavity, wherein the step of making the sealing material flow back into the cavity from the second gate includes a step of applying higher pressure to a second plunger for injecting the sealing material to the cavity from the second gate than pressure applied to a first plunger for injecting the sealing material to the cavity from the first gate. However, hardening the resin and removing any excess is well known in the art and would therefore be deemed obvious to one of ordinary skill in the art at the time of filing. Furthermore, it would be obvious to one of ordinary skill in the art at the time of filing to apply more pressure on the second plunger because the molten resin immediately starts to harden once the injection begins and more force would be required during the second plunger action. Regarding claim 5, ‘513 discloses the method of manufacturing the semiconductor device according to claim 1, as mentioned above. ‘513 does not explicitly disclose wherein the step of making the sealing material flow back into the cavity via the second gate includes a step of forming two or more curved parts in an elongate shape in a plan view of at least one metal wire in the plurality of metal wires. However, ‘513 does disclose wherein the sealing method is applied to a DIP type IC chip and that an SIP type IC chip or other types can be used in conjunction with changes in the mold structure, positions of injection ports, etc. as appropriate (paragraphs 0007-0010). Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to realize the claimed wire forming parts during the material flow back given normal implementation of ‘513s teachings. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Patent Application Publication 2002/0017738 discloses a semiconductor resin sealing method which incorporates back flow process. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS M MENZ whose telephone number is (571)272-1877. The examiner can normally be reached Monday-Friday 8:00am-5:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DOUGLAS M MENZ/ Primary Examiner, Art Unit 2897 1/24/26
Read full office action

Prosecution Timeline

Sep 18, 2023
Application Filed
Jan 24, 2026
Non-Final Rejection — §102, §103
Apr 01, 2026
Interview Requested
Apr 08, 2026
Applicant Interview (Telephonic)
Apr 08, 2026
Examiner Interview Summary

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
93%
With Interview (+4.6%)
2y 3m
Median Time to Grant
Low
PTA Risk
Based on 760 resolved cases by this examiner. Grant probability derived from career allow rate.

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