Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Response to Amendments/Arguments
Applicant's arguments, pages 6-7 of the remarks, filed 03/24/2026, with respect to 35 U.S.C 102(a)(1) rejections of claims 1 and 7 as unpatentable over US20220139911A1; Wei et al.; (hereinafter “Wei”) have been fully considered and are not found persuasive.
Applicant argues in pages 6-7 of the remarks that the structural dimensions in the drawings of Wei are not drawn to scale and Wei is silent on the specific dimensions of the gate structure which are not sufficient basis to conclude that the thickness of the bottom metal gate is larger than the middle metal gate of the gate structure. However, examiner respectfully disagrees.
Although Wei does not explicitly disclose exact dimensions or proportions of the figures, figures such as 3K-3O or 4A-4E (see figure 4E annotated below) of Wei do clearly show consistent relative thicknesses #T3/#T2 of metal gate portions between channels that would reasonably suggest or teach one of ordinary skill in the art. See MPEP 2125. Hence, the rejections are maintained.
Double Patenting
A rejection based on double patenting of the “same invention” type finds its support in the language of 35 U.S.C. 101 which states that “whoever invents or discovers any new and useful process... may obtain a patent therefor...” (Emphasis added). Thus, the term “same invention,” in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co., 151 U.S. 186 (1894); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Ockert, 245 F.2d 467, 114 USPQ 330 (CCPA 1957).
A statutory type (35 U.S.C. 101) double patenting rejection can be overcome by canceling or amending the claims that are directed to the same invention so they are no longer coextensive in scope. The filing of a terminal disclaimer cannot overcome a double patenting rejection based upon 35 U.S.C. 101.
Claims 1-4, 5-6, 7-10 and 11-13 provisionally rejected under 35 U.S.C. 101 as claiming the same invention as that of claims 1-4, 9-10, 11-14 and 18-20 of copending Application No. 18/824,706 (reference application). This is a provisional statutory double patenting rejection since the claims directed to the same invention have not in fact been patented.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 6-9 and 13 are rejected under 35 U.S.C. 102(a)(1) as being unpatentable over Wei.
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Regarding Claim 1, Wei teaches a field effect transistor (FET) structure (Figure 1, nano-FET), comprising:
a gate structure (#372, Figure 4E annotated), disposed between a first vertical source/drain (S/D) structure (#414-1, S/D regions) and a second vertical S/D structure (#414-2), the gate structure comprising a channel structure (#475) and a vertical metal gate structure (#372, gate electrode material), the channel structure comprising a plurality of vertically-stacked, horizontal channels (#475-1-#475-3, channels) connecting the first vertical S/D structure to the second vertical S/D structure horizontally through the vertical metal gate structure that at least partially surrounds the plurality of horizontal channels (#475-1 connects adjacent #414-1 and #414-2 through #372, wherein #372 partially surrounds #475-1); and
a backside inter-layer dielectric (ILD) layer (#380) disposed below the vertical metal gate structure (#372),
wherein a first thickness (#T3, Figure 4E annotated) of the vertical metal gate structure below a bottom channel (#475-1) of the plurality of horizontal channels is larger than a second thickness (#T2) of the vertical metal gate structure between adjacent channels (#475-2 and #475-3) of the plurality of horizontal channels.
Regarding Claim 2, Wei teaches a FET structure as described in claim 1, wherein Wei further teaches a third thickness (#T1, Figure 4E annotated) of the vertical metal gate structure (#372) above a top channel (#475-3) of the plurality of horizontal channels is larger than the second thickness (#T2) of the vertical metal gate structure between adjacent channels of the plurality of horizontal channels (#T1 > #T2).
Regarding Claim 3, Wei teaches a FET structure as described in claim 1, wherein Wei further teaches a backside contact structure (#483, Figure 4E annotated, backside gate contact) electrically coupled to the vertical metal gate structure through the backside ILD layer or through the backside ILD layer and a shallow trench isolation (STI) layer (#483 disposes through backside dielectric #480 and dielectric liner #364).
Regarding Claim 6, Wei teaches a FET structure as described in claim 1, wherein Wei further teaches a backside S/D via (#383, Figure 3R-S) connected to the first vertical S/D structure (#366, drain material) through the backside ILD layer (#380, backside dielectric).
Regarding Claim 7, Wei teaches a method for fabricating a field effect transistor (FET) structure (Figure 2A-B), the method comprising:
providing a gate structure (#372, Figure 4E annotated), disposed between a first vertical source/drain (S/D) structure (#414-1, S/D regions) and a second vertical S/D structure (#414-2), the gate structure comprising a channel structure (#475) and a vertical metal gate structure (#372, gate electrode material), the channel structure comprising a plurality of vertically-stacked, horizontal channels (#475-1-#475-3, channels) connecting the first vertical S/D structure to the second vertical S/D structure horizontally through the vertical metal gate structure that at least partially surrounds the plurality of horizontal channels (#475-1 connects adjacent #414-1 and #414-2 through #372, wherein #372 partially surrounds #475-1); and
a backside inter-layer dielectric (ILD) layer (#380) disposed below the vertical metal gate structure (#372),
wherein a first thickness (#T1, Figure 4e annotated) of the vertical metal gate structure below a bottom channel (#475-1) of the plurality of horizontal channels is larger than a second thickness (#T2) of the vertical metal gate structure between adjacent channels (#475-2 and #475-3) of the plurality of horizontal channels (#T1 > #T2).
Regarding Claim 8, Wei teaches a method for fabricating a FET structure as described in claim 7, wherein Wei further teaches a third thickness (#T1, Figure 4E annotated) of the vertical metal gate structure (#372) above a top channel (#475-3) of the plurality of horizontal channels is larger than the second thickness (#T2) of the vertical metal gate structure between adjacent channels of the plurality of horizontal channels (#T1 > #T2).
Regarding Claim 9, Wei teaches a method for fabricating a FET structure as described in claim 7, wherein Wei further teaches a backside contact structure (#483, Figure 4E annotated, backside gate contact) electrically coupled to the vertical metal gate structure through the backside ILD layer or through the backside ILD layer and a shallow trench isolation (STI) layer (#483 disposes through backside dielectric #480 and dielectric liner #364).
Regarding Claim 13, Wei teaches a method for fabricating a FET structure as described in claim 7, wherein Wei further teaches providing a backside S/D via (#383, Figure 3R-S) connected to the first vertical S/D structure (#366, drain material) through the backside ILD layer (#380, backside dielectric).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 4, 10 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Wei in view of US20210375761A1; Chang et al.; (hereinafter “Chang”).
Regarding Claim 4, Wei teaches a FET structure as described in claim 3, wherein Wei further teaches the backside contact structure (#483, Figure 4E annotated) is electrically coupled to a backside structure (#482, backside power rail) disposed below the backside ILD layer.
Wei does not explicitly teach a backside metallization structure.
However, Chang teaches a FET structure (Figure 1, nano-FET) comprises a backside metallization structure (#135/135S, Figure 31D, [0107-0108], conductive/signal lines connected to backside gate via #164).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Wei with the teaching of Chang, as it would be a simple substitution of one known element (backside power rail of Wei) for another (conductive lines of Chang) in comparable devices to obtain predictable results (provide signal/power routing to backside gate contact). See MPEP 2143(I)(B).
Regarding Claim 10, Wei teaches a method for fabricating a FET structure as described in claim 9, wherein Wei further teaches the backside contact structure (#483, Figure 4E annotated) is electrically coupled to a backside structure (#482, backside power rail) disposed below the backside ILD layer.
Wei does not explicitly teach a backside metallization structure.
However, Chang teaches a FET structure (Figure 1, nano-FET) comprises a backside metallization structure (#135/135S, Figure 31D, [0107-0108], conductive/signal lines connected to backside gate via #164).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Wei with the teaching of Chang, as it would be a simple substitution of one known element (backside power rail of Wei) for another (conductive lines of Chang) in comparable devices to obtain predictable results (provide signal/power routing to backside gate contact). See MPEP 2143(I)(B).
Regarding Claim 12, Wei teaches a method for fabricating a FET structure as described in claim 9, wherein Wei further teaches providing the backside contact structure electrically coupled to the vertical metal gate structure through the backside ILD layer or through the backside ILD layer and the STI layer (Figure 4E annotated, see rejection of claim 9) comprises:
etching the backside ILD layer to expose a dielectric layer of the vertical metal gate structure below the bottom channel of the plurality of horizontal channels (Figure 4A, opening #479 is etched to expose gate dielectric material #374 below channel #475-1);
performing a metallization process to create the backside contact structure electrically coupled to the vertical metal gate structure below the bottom channel of the plurality of horizontal channels (Figure 4B, [0125], opening #479 is filled with conductive material #378 to form backside gate contact #483).
Wei does not explicitly teach etching the dielectric layer to expose a gate electrode of the vertical metal gate structure below the bottom channel of the plurality of horizontal channels.
However, Chang teaches etching the dielectric layer (#100, Figure 31D or 28A, dielectric layer) to expose a gate electrode (#102) of the vertical metal gate structure below the bottom channel (#54A) of the plurality of horizontal channels (backside gate via #164 extends through #100 connecting to #102).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Wei with the teaching of Chang, as it would be a simple substitution of one known element (backside gate contact of Wei) for another (backside gate via of Chang) in comparable devices to obtain predictable results (provide backside contact to gate structure). See MPEP 2143(I)(B).
Claims 5 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Wei in view of US20240112984A1; Li et al.; (hereinafter “Li”).
Regarding Claim 5, Wei teaches a FET structure as described in claim 3, wherein Wei further teaches the backside contact structure (#483, Figure 4E annotated).
Wei does not explicitly teach a backside gate isolation tiedown.
However, Li teaches a FET structure ([0003]), comprising a backside gate isolation tiedown (#VBPR, Figure 18C, [0079], via-to-backside power rail gate contact providing gate tied down).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Wei with the teaching of Li in order to reduce the negative effect from diffusion breaks, avoid epitaxial damage, increase device performance and minimize area loss according to Li, [0050].
Regarding Claim 11, Wei teaches a method for fabricating a FET structure as described in claim 7, wherein Wei further teaches the backside contact structure (#483, Figure 4E annotated).
Wei does not explicitly teach a backside gate isolation tiedown.
However, Li teaches a FET structure ([0003]), comprising a backside gate isolation tiedown (#VBPR, Figure 18C, [0079], via-to-backside power rail gate contact providing gate tied down).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Wei with the teaching of Li in order to reduce the negative effect from diffusion breaks, avoid epitaxial damage, increase device performance and minimize area loss according to Li, [0050].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US20220223626A1 – Figures 2A-3A and [0059], different thickness #H1-H3 of gate portion #P01-P03.
US20230042548A1 – Figures 18-27
US20190378911A1 – Figure 2
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/TIEN TRAN/Examiner, Art Unit 2812
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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