Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 08/18/2026 has been entered.
Response to Amendments/Arguments
Applicant's amendment to claims 1 and 7 and corresponding arguments, pages 6-8 of the remarks, filed 08/18/2026, with respect to 35 U.S.C 102(a)(1) rejections of the claims as unpatentable over US20220139911A1; Wei et al.; (hereinafter “Wei”) have been fully considered and are not found persuasive. (See 35 U.S.C. 102/103 of amended claim 1 below)
Applicant argues in pages 7-8 of the remarks that the structural dimensions in the drawings of Wei are inconsistent and not drawn to scale and Wei is silent on the specific dimensions of a gate structure which are not sufficient basis to conclude that a thickness of a bottom metal gate portion is larger than a middle metal gate portion of the gate structure. Furthermore, applicant argues that MPEP 2125 does not allow patent drawings to be relied upon to teach dimensions of a structure. However, examiner respectfully disagrees.
Although Wei does not explicitly disclose specific dimensions or proportions of the gate structure and there’s a minor inconsistency between portions of gate structure as shown in Figures 3O and 3P, all figures including Figures 3O-3P (see figures 3O-3P or 4E of Wei annotated below) show a clear consistency in the difference of the relative thicknesses #T1-T3 of metal gate portions between channels. Accordingly, one of ordinary skill in the art would reasonably recognize from the drawings and understand that the metal gate portions are of different thicknesses, and in this case, the thickness of the bottom metal gate portion is greater than the middle metal gate portion.
Furthermore, as recited in MPEP 2125 (I): “Drawings and pictures can anticipate claims if they clearly show the structure which is claimed…When the reference is a utility patent, it does not matter that the feature shown is unintended or unexplained in the specification. The drawings must be evaluated for what they reasonably disclose and suggest to one of ordinary skill in the art” and in MPEP 2125 (II): “When the reference does not disclose that the drawings are to scale and is silent as to dimensions…the description of the article pictured can be relied on, in combination with the drawings, for what they would reasonably teach one of ordinary skill in the art”, in this case, one of ordinary skill in the art would reasonably recognize from the consistency in the drawings of Wei and understand that the metal gate portions are of different thicknesses such as one portion is greater than other without details of specific ratio/dimension.
Hence, the rejections are maintained.
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Double Patenting
A rejection based on double patenting of the “same invention” type finds its support in the language of 35 U.S.C. 101 which states that “whoever invents or discovers any new and useful process... may obtain a patent therefor...” (Emphasis added). Thus, the term “same invention,” in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co., 151 U.S. 186 (1894); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Ockert, 245 F.2d 467, 114 USPQ 330 (CCPA 1957).
A statutory type (35 U.S.C. 101) double patenting rejection can be overcome by canceling or amending the claims that are directed to the same invention so they are no longer coextensive in scope. The filing of a terminal disclaimer cannot overcome a double patenting rejection based upon 35 U.S.C. 101.
Claims 1, 2, 4, 6, 7, 8, 10, 12 and 13 provisionally rejected under 35 U.S.C. 101 as claiming the same invention as that of claims 3, 2, 4, 10, 13, 12, 14, 19 and 20 of copending Application No. 18/824,706 (reference application). This is a provisional statutory double patenting rejection since the claims directed to the same invention have not in fact been patented.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4, 6-8, 10 and 13 are rejected under 35 U.S.C. 102(a)(1) as being unpatentable over Wei.
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Regarding Claim 1 (currently amended), Wei teaches a field effect transistor (FET) structure (Figure 1, nano-FET), comprising:
a gate structure (#372, Figure 4E of Wei annotated), disposed between a first vertical source/drain (S/D) structure (#414-1, S/D regions) and a second vertical S/D structure (#414-2), the gate structure comprising a channel structure (#475) and a vertical metal gate structure (#372, gate electrode material), the channel structure comprising a plurality of vertically-stacked, horizontal channels (#475-1-#475-3, channels) connecting the first vertical S/D structure to the second vertical S/D structure horizontally through the vertical metal gate structure that at least partially surrounds the plurality of horizontal channels (#475-1 connects adjacent #414-1 and #414-2 through #372, wherein #372 partially surrounds #475-1); and
a backside inter-layer dielectric (ILD) layer (#380) disposed below the vertical metal gate structure (#372); and
a backside contact structure (#483) electrically coupled to the vertical metal gate structure (#372) through the backside ILD layer (#380) or through the backside ILD layer and a shallow trench isolation (STI) layer, which connects the gate structure (#372) to signal routing (in this case, signal routing can be reasonably interpreted as any metal structure, such as backside power rail #382/#482, connecting to the gate intended for routing power/electrical signal and not limiting to data signal).
wherein a first thickness (#T3, Figure 4E of Wei annotated) of the vertical metal gate structure below a bottom channel (#475-1) of the plurality of horizontal channels is larger than a second thickness (#T2) of the vertical metal gate structure between adjacent channels (#475-2 and #475-3) of the plurality of horizontal channels.
Regarding Claim 2, Wei teaches the FET structure as described in claim 1, wherein Wei further teaches a third thickness (#T1, Figure 4E of Wei annotated) of the vertical metal gate structure (#372) above a top channel (#475-3) of the plurality of horizontal channels is larger than the second thickness (#T2) of the vertical metal gate structure between adjacent channels of the plurality of horizontal channels (#T1 > #T2).
Regarding Claim 4 (currently amended), Wei teaches the FET structure as described in claim 1, wherein Wei further teaches the backside contact structure (#483, Figure 4E of Wei annotated) is electrically coupled to a backside metallization structure (#482) disposed below the backside ILD (#380).
Regarding Claim 6, Wei teaches the FET structure as described in claim 1, wherein Wei further teaches a backside S/D via (#383, Figure 3R-S) connected to the first vertical S/D structure (#366, drain material) through the backside ILD layer (#380, backside dielectric).
Regarding Claim 7 (currently amended), Wei teaches a method for fabricating a field effect transistor (FET) structure (Figure 2A-B), the method comprising:
providing a gate structure (#372, Figure 4E of Wei annotated), disposed between a first vertical source/drain (S/D) structure (#414-1, S/D regions) and a second vertical S/D structure (#414-2), the gate structure comprising a channel structure (#475) and a vertical metal gate structure (#372, gate electrode material), the channel structure comprising a plurality of vertically-stacked, horizontal channels (#475-1-#475-3, channels) connecting the first vertical S/D structure to the second vertical S/D structure horizontally through the vertical metal gate structure that at least partially surrounds the plurality of horizontal channels (#475-1 connects adjacent #414-1 and #414-2 through #372, wherein #372 partially surrounds #475-1); and
providing a backside inter-layer dielectric (ILD) layer (#380) disposed below the vertical metal gate structure (#372),
providing a backside contact structure (#483) electrically coupled to the vertical metal gate structure (#372) through the backside ILD layer (#380) or through the backside ILD layer and a shallow trench isolation (STI) layer, which connects the gate structure (#372) to signal routing (in this case, signal routing can be reasonably interpreted as any metal structure, such as backside power rail #382/#482, connecting to the gate intended for routing power/electrical signal and not limiting to data signal).
wherein a first thickness (#T1, Figure 4E of Wei annotated) of the vertical metal gate structure below a bottom channel (#475-1) of the plurality of horizontal channels is larger than a second thickness (#T2) of the vertical metal gate structure between adjacent channels (#475-2 and #475-3) of the plurality of horizontal channels (#T1 > #T2).
Regarding Claim 8, Wei teaches the method as described in claim 7, wherein Wei further teaches a third thickness (#T1, Figure 4E of Wei annotated) of the vertical metal gate structure (#372) above a top channel (#475-3) of the plurality of horizontal channels is larger than the second thickness (#T2) of the vertical metal gate structure between adjacent channels of the plurality of horizontal channels (#T1 > #T2).
Regarding Claim 10 (currently amended), Wei teaches the method as described in claim 7, wherein Wei further teaches the backside contact structure (#483, Figure 4E of Wei annotated) is electrically coupled to a backside metallization structure (#482, backside power rail) disposed below the backside ILD layer (#380).
Regarding Claim 13, Wei teaches the method as described in claim 7, wherein Wei further teaches providing a backside S/D via (#383, Figure 3R-S) connected to the first vertical S/D structure (#366, drain material) through the backside ILD layer (#380, backside dielectric).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2, 4, 6-8, 10 and 13 are rejected under 35 U.S.C. 102(a)(1) (see above 35 U.S.C. 102 rejections of the claims) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Wei.
Regarding Claim 1 (currently amended), Wei teaches a field effect transistor (FET) structure (Figure 1, nano-FET), comprising:
a gate structure (#372, Figure 4E), disposed between a first vertical source/drain (S/D) structure (#414-1, S/D regions) and a second vertical S/D structure (#414-2), the gate structure comprising a channel structure (#475) and a vertical metal gate structure (#372, gate electrode material), the channel structure comprising a plurality of vertically-stacked, horizontal channels (#475-1-#475-3, channels) connecting the first vertical S/D structure to the second vertical S/D structure horizontally through the vertical metal gate structure that at least partially surrounds the plurality of horizontal channels (#475-1 connects adjacent #414-1 and #414-2 through #372, wherein #372 partially surrounds #475-1); and
a backside inter-layer dielectric (ILD) layer (#380) disposed below the vertical metal gate structure (#372); and
a backside contact structure (#483) electrically coupled to the vertical metal gate structure (#372) through the backside ILD layer (#380) or through the backside ILD layer and a shallow trench isolation (STI) layer,
wherein a first thickness (#T3, Figure 4E of Wei annotated) of the vertical metal gate structure below a bottom channel (#475-1) of the plurality of horizontal channels is larger than a second thickness (#T2) of the vertical metal gate structure between adjacent channels (#475-2 and #475-3) of the plurality of horizontal channels.
Wei does not explicitly teach the backside contact structure connecting the gate structure to signal routing (in the case where signal routing is interpreted as signal line for routing data signal).
However, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention of Wei by a simple substitution of one known element (backside power rail structure of Wei) for another (backside signal line/routing structure) to obtain predictable results (provide obvious variants of backside contact structure to the gate structure, see also [0040] of instant application regarding alternative purposes of backside contact for signal routing or power routing). See MPEP 2143(I)(B).
Regarding Claim 2, Wei teaches the FET structure as described in claim 1, wherein Wei further teaches a third thickness (#T1, Figure 4E of Wei annotated) of the vertical metal gate structure (#372) above a top channel (#475-3) of the plurality of horizontal channels is larger than the second thickness (#T2) of the vertical metal gate structure between adjacent channels of the plurality of horizontal channels (#T1 > #T2).
Regarding Claim 4 (currently amended), Wei teaches the FET structure as described in claim 1, wherein Wei further teaches the backside contact structure (#483, Figure 4E of Wei annotated) is electrically coupled to a backside metallization structure (#482) disposed below the backside ILD (#380).
Regarding Claim 6, Wei teaches the FET structure as described in claim 1, wherein Wei further teaches a backside S/D via (#383, Figure 3R-S) connected to the first vertical S/D structure (#366, drain material) through the backside ILD layer (#380, backside dielectric).
Regarding Claim 7 (currently amended), Wei teaches a method for fabricating a field effect transistor (FET) structure (Figure 2A-B), the method comprising:
providing a gate structure (#372, Figure 4E of Wei annotated), disposed between a first vertical source/drain (S/D) structure (#414-1, S/D regions) and a second vertical S/D structure (#414-2), the gate structure comprising a channel structure (#475) and a vertical metal gate structure (#372, gate electrode material), the channel structure comprising a plurality of vertically-stacked, horizontal channels (#475-1-#475-3, channels) connecting the first vertical S/D structure to the second vertical S/D structure horizontally through the vertical metal gate structure that at least partially surrounds the plurality of horizontal channels (#475-1 connects adjacent #414-1 and #414-2 through #372, wherein #372 partially surrounds #475-1); and
providing a backside inter-layer dielectric (ILD) layer (#380) disposed below the vertical metal gate structure (#372),
providing a backside contact structure (#483) electrically coupled to the vertical metal gate structure (#372) through the backside ILD layer (#380) or through the backside ILD layer and a shallow trench isolation (STI) layer,
wherein a first thickness (#T1, Figure 4E of Wei annotated) of the vertical metal gate structure below a bottom channel (#475-1) of the plurality of horizontal channels is larger than a second thickness (#T2) of the vertical metal gate structure between adjacent channels (#475-2 and #475-3) of the plurality of horizontal channels (#T1 > #T2).
Wei does not explicitly teach the backside contact structure connecting the gate structure to signal routing (in the case where signal routing is interpreted as signal line for routing data signal).
However, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention of Wei by a simple substitution of one known element (backside power rail structure of Wei) for another (backside signal line/routing structure) to obtain predictable results (provide obvious variants of backside contact structure to the gate structure, see also [0040] of instant application regarding alternative purposes of backside contact for signal routing or power routing). See MPEP 2143(I)(B).
Regarding Claim 8, Wei teaches the method as described in claim 7, wherein Wei further teaches a third thickness (#T1, Figure 4E of Wei annotated) of the vertical metal gate structure (#372) above a top channel (#475-3) of the plurality of horizontal channels is larger than the second thickness (#T2) of the vertical metal gate structure between adjacent channels of the plurality of horizontal channels (#T1 > #T2).
Regarding Claim 10 (currently amended), Wei teaches the method as described in claim 7, wherein Wei further teaches the backside contact structure (#483, Figure 4E of Wei annotated) is electrically coupled to a backside metallization structure (#482, backside power rail) disposed below the backside ILD layer (#380).
Regarding Claim 13, Wei teaches the method as described in claim 7, wherein Wei further teaches providing a backside S/D via (#383, Figure 3R-S) connected to the first vertical S/D structure (#366, drain material) through the backside ILD layer (#380, backside dielectric).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Wei in view of US20210375761A1; Chang et al.; (hereinafter “Chang”).
Regarding Claim 12 (currently amended), Wei teaches the method as described in claim 7, wherein Wei further teaches providing the backside contact structure electrically coupled to the vertical metal gate structure through the backside ILD layer or through the backside ILD layer and the STI layer (Figures 4A-E, see rejection of claim 7) comprises:
etching the backside ILD layer to expose a dielectric layer of the vertical metal gate structure below the bottom channel of the plurality of horizontal channels (Figure 4A, opening #479 is etched to expose gate dielectric material #374 below channel #475-1);
performing a metallization process to create the backside contact structure electrically coupled to the vertical metal gate structure below the bottom channel of the plurality of horizontal channels (Figure 4B, [0125], opening #479 is filled with conductive material #378 to form backside gate contact #483).
Wei does not explicitly teach etching the dielectric layer to expose a gate electrode of the vertical metal gate structure below the bottom channel of the plurality of horizontal channels.
However, Chang teaches a method of forming a nano-FET (Figure 1) comprising etching the dielectric layer (#100, Figures 31D or 28B, gate dielectric layer) to expose a gate electrode (#102) of the vertical metal gate structure below the bottom channel (#54A) of the plurality of horizontal channels.
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Wei with the teaching of Chang, as it would be a simple substitution of one known element (backside gate contact of Wei) for another (backside gate via of Chang) in comparable devices to obtain predictable results (provide backside contact to gate structure). See MPEP 2143(I)(B).
Conclusion
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/TIEN TRAN/Examiner, Art Unit 2812
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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