DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 9/18/2023, 2/19/2025 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7, 10-17 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lai (US 2023/0067311) in view of Chen (US 2021/0375853), and further in view of Tsao (US 2023/0223276).
Regarding claim 1, Lai discloses, in at least figures 1A, 2A, 6A, 7A-7I, and related text, a semiconductor device comprising:
a plurality of integrated circuit cells (dummy gate 210 specify the isolation regions in the neighboring cells, [36], [45]), each of the plurality of integrated circuit cells comprising:
a plurality of gate structures (gB2/gB1/gA1/gA2, [45]) spaced apart from each other by one of a first plurality of source/drain (S/D) structures (source/drain regions in 80p/80n, [46], [48]), each gate structure (gB2/gB1/gA1/gA2, [45]) comprising a channel structure (80p/80n, [46], [48]) and a gate structure (gB2/gB1/gA1/gA2, [45]), the channel structure (80p/80n, [46], [48]) comprising at least one channel extending through the metal gate structure (gB2/gB1/gA1/gA2, [45]) and connecting adjacent S/D structures in the first plurality of S/D structures (source/drain regions in 80p/80n, [46], [48]) to each other, wherein at least one of the plurality of gate structures (gB2/gB1/gA1/gA2, [45]) forms a gate-all-around (GAA) field effect transistor (FET) (figures);
a frontside source/drain contact (FSDC) structure (VD, [52]) electrically connecting to a top surface of at least one of the first plurality of S/D structures (80p, 632p, [52], figure 7A);
a frontside contact (VG, [52]) over active gate (FSCOAG) structure (gB2/gB1/gA1/gA2, [45]) electrically connecting to a top surface of at least one of the plurality of gate structures (gB2, figure 7B);
a frontside metal zero (FM0) interconnect layer (layer of 20F/620F/642F/644F/646F, [51]), comprising a plurality of parallel FM0 interconnects (20F/620F/642F/644F/646F, [51]), at least one being electrically connected to the FSDC structure (VD, [52]) or the FSCOAG structure (gB2/gB1/gA1/gA2, [45]) (figures 7A, 7B);
a backside source/drain contact (BSDC) structure (VB, [52]) electrically connecting to a bottom surface of at least one of the first plurality of S/D structures (80n, 632n, [52], figure 7A);
a backside contact (BVG, [52]) over active gate (BSCOAG) structure (gB2/gB1/gA1/gA2, [45]) electrically connecting to a bottom surface of at least one of the plurality of gate structures (gB1, [52], figure 7D); and
a backside metal zero (BM0) interconnect layer (layer of 20B/622B/624B/642B/644B, [51]), comprising a plurality of parallel BM0 interconnects (20B/622B/624B/642B/644B, [51]), at least one being electrically connected to the BSDC structure (VB, [52]) or the BSCOAG structure (gB2/gB1/gA1/gA2, [45]) (figures 7A, 7D).
Lai does not explicitly disclose each gate structure comprising a channel structure and a metal gate structure, the channel structure comprising at least one channel extending through the metal gate structure; a frontside inter-layer dielectric (FS-ILD) layer disposed on the plurality of gate structures and the first plurality of S/D structures; a frontside metal zero (FM0) interconnect layer disposed on the FS-ILD layer; a backside inter-layer dielectric (BS-ILD) layer disposed on the plurality of gate structures and the first plurality of S/D structures; a backside metal zero (BM0) interconnect layer disposed on the BS-ILD layer.
Chen teaches, in at least figure 1B and related text, the device comprising each gate structure (151, [37]) comprising a channel structure (152, [37]) and a metal gate structure ([37]), the channel structure (152, [37]) comprising at least one channel extending through the metal gate structure (151, [37]), for the purpose of providing various portions of an active region in an IC device electrically coupled to each other both on a front side and on a back side of the IC device thereby reducing resistances of connections between the electrically coupled portions of the active region ([19]).
Tsao teaches, in at least figure 12 and related text, the device comprising a frontside inter-layer dielectric (FS-ILD) layer (242, [50]) disposed on the plurality of gate structures (250, [52]) and the first plurality of S/D structures (240-1S1/240-1S2/240-2S1/240-2S2, [48]); a frontside metal zero (FM0) interconnect layer (264G1/264S1/264S2/264S3, [57]) disposed on the FS-ILD layer (242, [50]); a backside inter-layer dielectric (BS-ILD) layer (204, [34]) disposed on the plurality of gate structures (250, [52]) and the first plurality of S/D structures (240-1S1/240-1S2/240-2S1/240-2S2, [48]); a backside metal zero (BM0) interconnect layer (layers of 284P/284TG/284 closest to 204, [63], figure) disposed on the BS-ILD layer (204, [34]), for the purpose of providing back-side interconnect structure for the routings for the isolation field-effect transistor device and the power circuits for other field-effect transistor devices thereby reducing the area of the resulting semiconductor structure ([32]).
Lai, Chen, and Tsao are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lai with the specified features of Chen and Tsao because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Lai to have the each gate structure comprising a channel structure and a metal gate structure, the channel structure comprising at least one channel extending through the metal gate structure, as taught by Chen and the frontside inter-layer dielectric (FS-ILD) layer disposed on the plurality of gate structures and the first plurality of S/D structures; the frontside metal zero (FM0) interconnect layer disposed on the FS-ILD layer; the backside inter-layer dielectric (BS-ILD) layer disposed on the plurality of gate structures and the first plurality of S/D structures; the backside metal zero (BM0) interconnect layer disposed on the BS-ILD layer, as taught by Tsao, for the purpose of providing various portions of an active region in an IC device electrically coupled to each other both on a front side and on a back side of the IC device thereby reducing resistances of connections between the electrically coupled portions of the active region ([19], Chen) and providing back-side interconnect structure for the routings for the isolation field-effect transistor device and the power circuits for other field-effect transistor devices thereby reducing the area of the resulting semiconductor structure ([32], Tsao).
Regarding claim 2, Lai in view of Chen and Tsao discloses the semiconductor device of claim 1 as described above.
Lai further discloses, in at least figures 1A, 2A, 6A, 7A-7I, and related text, the FM0 interconnect layer (layer of 20F/620F/642F/644F/646F, [51]) comprises six or fewer parallel FM0 interconnects (20F/620F/642F/644F/646F, [51]) and wherein the BM0 interconnect layer (layer of 20B/622B/624B/642B/644B, [51]) comprises six or fewer parallel BM0 interconnects (20B/622B/624B/642B/644B, [51]).
Regarding claim 3, Lai in view of Chen and Tsao discloses the semiconductor device of claim 1 as described above.
Lai further discloses, in at least figures 1A, 2A, 6A, 7A-7I, and related text, the FM0 interconnect layer (layer of 20F/620F/642F/644F/646F, [51]) comprises five or fewer parallel FM0 interconnects (20F/620F/642F/644F/646F, [51]) and wherein the BM0 interconnect layer (layer of 20B/622B/624B/642B/644B, [51]) comprises five or fewer parallel BM0 interconnects (20B/622B/624B/642B/644B, [51]).
Regarding claim 4, Lai in view of Chen and Tsao discloses the semiconductor device of claim 1 as described above.
Lai further discloses, in at least figures 1A, 2A, 6A, 7A-7I, and related text, the FM0 interconnect layer (layer of 20F/620F/642F/644F/646F, [51]) comprises four or fewer parallel FM0 interconnects (20F/620F/642F/644F/646F, [51]) and wherein the BM0 interconnect layer (layer of 20B/622B/624B/642B/644B, [51]) comprises four or fewer parallel BM0 interconnects (20B/622B/624B/642B/644B, [51]).
Regarding claim 5, Lai in view of Chen and Tsao discloses the semiconductor device of claim 1 as described above.
Lai further discloses, in at least figures 1A, 2A, 6A, 7A-7I, and related text, the FM0 interconnect layer (layer of 20F/620F/642F/644F/646F, [51]) comprises three or fewer parallel FM0 interconnects (20F/620F/642F/644F/646F, [51]) and wherein the BM0 interconnect layer (layer of 20B/622B/624B/642B/644B, [51]) comprises three or fewer parallel BM0 interconnects (20B/622B/624B/642B/644B, [51]).
Regarding claim 6, Lai in view of Chen and Tsao discloses the semiconductor device of claim 1 as described above.
Lai in view of Chen does not explicitly disclose each of the first plurality of S/D structures comprises an EPI layer.
Tsao teaches, in at least figure 12 and related text, the device comprising each of the first plurality of S/D structures (240-1S1/240-1S2/240-2S1/240-2S2, [48]) comprises an EPI layer ([48]), for the purpose of eliminating substrate leakage ([48]).
Lai, Chen, and Tsao are analogous art because they all are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lai in view of Chen with the specified features of Tsao because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Lai in view of Chen to have the each of the first plurality of S/D structures comprises an EPI layer, as taught by Tsao, for the purpose of providing larger source/drain and eliminating substrate leakage ([48], Tsao).
Regarding claim 7, Lai in view of Chen and Tsao discloses the semiconductor device of claim 1 as described above.
Lai in view of Tsao does not explicitly disclose the metal gate structure comprises a high-K dielectric layer at least partially surrounding a work function metal layer.
Chen teaches, in at least figure 1B and related text, the metal gate structure (151, [37]) comprises a high-K dielectric layer at least partially surrounding a work function metal layer ([37], figure), for the purpose of providing better controllability of gate for carriers in channel and tunning threshold voltage of transistor.
Lai, Chen, and Tsao are analogous art because they all are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lai in view of Tsao with the specified features of Chen because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Lai in view of Tsao to have the metal gate structure comprising a high-K dielectric layer at least partially surrounding a work function metal layer, as taught by Chen, for the purpose of providing better controllability of gate for carriers in channel and tunning threshold voltage of transistor.
Regarding claim 10, Lai in view of Chen and Tsao discloses the semiconductor device of claim 1 as described above.
Lai further discloses, in at least figures 1A, 2A, 6A, 7A-7I, and related text, the plurality of gate structures (gB2/gB1/gA1/gA2, [45]) are spaced apart from each other by one of a second plurality of S/D structures (source/drain regions in 80n, [48]) offset from the first plurality of S/D structures (source/drain regions in 80p, [46]), each gate structure (gB2/gB1/gA1/gA2, [45]) comprising a second channel structure (80n, [48]) and a second gate structure (gB2/gB1/gA1/gA2, [45]), the second channel structure (gB2/gB1/gA1/gA2, [45]) comprising at least one channel connecting (80n, [48]) adjacent S/D structures in the second plurality of S/D structures (source/drain regions in 80n, [48]) to each other.
Lai in view of Tsao does not explicitly disclose each gate structure comprising a second channel structure and a second metal gate structure.
Chen further teaches, in at least figure 1B and related text, each gate structure (151, [37]) comprising a second channel structure (152, [37]) and a second metal gate structure ([37]), for the purpose of providing better controllability of gate for carriers in channels.
Lai, Chen, and Tsao are analogous art because they all are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lai in view of Tsao with the specified features of Chen because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Lai in view of Tsao to have each gate structure comprising a second channel structure and a second metal gate structure, as taught by Chen, for the purpose of providing better controllability of gate for carriers in channels.
Regarding claim 11, Lai discloses, in at least figures 1A, 2A, 6A, 7A-7I, and related text, a method for fabricating a semiconductor device, the method comprising:
providing a plurality of integrated circuit cells (dummy gate 210 specify the isolation regions in the neighboring cells, [36], [45]), comprising, for each of the plurality of integrated circuit cells:
providing a plurality of gate structures (gB2/gB1/gA1/gA2, [45]) spaced apart from each other by one of a first plurality of source/drain (S/D) structures (source/drain regions in 80p/80n, [46], [48]), each gate structure (gB2/gB1/gA1/gA2, [45]) comprising a channel structure (80p/80n, [46], [48]) and a gate structure (gB2/gB1/gA1/gA2, [45]), the channel structure (80p/80n, [46], [48]) comprising at least one channel extending through the metal gate structure (gB2/gB1/gA1/gA2, [45]) and connecting adjacent S/D structures in the first plurality of S/D structures (source/drain regions in 80p/80n, [46], [48]) to each other, wherein at least one of the plurality of gate structures (gB2/gB1/gA1/gA2, [45]) forms a gate-all-around (GAA) field effect transistor (FET) (figures);
providing a frontside source/drain contact (FSDC) structure (VD, [52]) electrically connecting to a top surface of at least one of the first plurality of S/D structures (80p, 632p, [52], figure 7A);
providing a frontside contact (VG, [52]) over active gate (FSCOAG) structure (gB2/gB1/gA1/gA2, [45]) electrically connecting to a top surface of at least one of the plurality of gate structures (gB2, figure 7B);
providing a frontside metal zero (FM0) interconnect layer (layer of 20F/620F/642F/644F/646F, [51]), comprising a plurality of parallel FM0 interconnects (20F/620F/642F/644F/646F, [51]), at least one being electrically connected to the FSDC structure (VD, [52]) or the FSCOAG structure (gB2/gB1/gA1/gA2, [45]) (figures 7A, 7B);
providing a backside source/drain contact (BSDC) structure (VB, [52]) electrically connecting to a bottom surface of at least one of the first plurality of S/D structures (80n, 632n, [52], figure 7A);
providing a backside contact (BVG, [52]) over active gate (BSCOAG) structure (gB2/gB1/gA1/gA2, [45]) electrically connecting to a bottom surface of at least one of the plurality of gate structures (gB1, [52], figure 7D); and
providing a backside metal zero (BM0) interconnect layer (layer of 20B/622B/624B/642B/644B, [51]), comprising a plurality of parallel BM0 interconnects (20B/622B/624B/642B/644B, [51]), at least one being electrically connected to the BSDC structure (VB, [52]) or the BSCOAG structure (gB2/gB1/gA1/gA2, [45]) (figures 7A, 7D).
Lai does not explicitly disclose each gate structure comprising a channel structure and a metal gate structure, the channel structure comprising at least one channel extending through the metal gate structure; providing a frontside inter-layer dielectric (FS-ILD) layer disposed on the plurality of gate structures and the first plurality of S/D structures; providing a frontside metal zero (FM0) interconnect layer disposed on the FS-ILD layer; providing a backside inter-layer dielectric (BS-ILD) layer disposed on the plurality of gate structures and the first plurality of S/D structures; providing a backside metal zero (BM0) interconnect layer disposed on the BS-ILD layer.
Chen teaches, in at least figure 1B and related text, the method comprising each gate structure (151, [37]) comprising a channel structure (152, [37]) and a metal gate structure ([37]), the channel structure (152, [37]) comprising at least one channel extending through the metal gate structure (151, [37]), for the purpose of providing various portions of an active region in an IC device electrically coupled to each other both on a front side and on a back side of the IC device thereby reducing resistances of connections between the electrically coupled portions of the active region ([19]).
Tsao teaches, in at least figure 12 and related text, the method comprising providing a frontside inter-layer dielectric (FS-ILD) layer (242, [50]) disposed on the plurality of gate structures (250, [52]) and the first plurality of S/D structures (240-1S1/240-1S2/240-2S1/240-2S2, [48]); providing a frontside metal zero (FM0) interconnect layer (264G1/264S1/264S2/264S3, [57]) disposed on the FS-ILD layer (242, [50]); providing a backside inter-layer dielectric (BS-ILD) layer (204, [34]) disposed on the plurality of gate structures (250, [52]) and the first plurality of S/D structures (240-1S1/240-1S2/240-2S1/240-2S2, [48]); providing a backside metal zero (BM0) interconnect layer (layers of 284P/284TG/284 closest to 204, [63], figure) disposed on the BS-ILD layer (204, [34]), for the purpose of providing back-side interconnect structure for the routings for the isolation field-effect transistor device and the power circuits for other field-effect transistor devices thereby reducing the area of the resulting semiconductor structure ([32]).
Lai, Chen, and Tsao are analogous art because they both are directed to method for forming a semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lai with the specified features of Chen and Tsao because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method disclosed in Lai to have the each gate structure comprising a channel structure and a metal gate structure, the channel structure comprising at least one channel extending through the metal gate structure, as taught by Chen and the providing a frontside inter-layer dielectric (FS-ILD) layer disposed on the plurality of gate structures and the first plurality of S/D structures; the providing a frontside metal zero (FM0) interconnect layer disposed on the FS-ILD layer; the providing a backside inter-layer dielectric (BS-ILD) layer disposed on the plurality of gate structures and the first plurality of S/D structures; the providing a backside metal zero (BM0) interconnect layer disposed on the BS-ILD layer, as taught by Tsao, for the purpose of providing various portions of an active region in an IC device electrically coupled to each other both on a front side and on a back side of the IC device thereby reducing resistances of connections between the electrically coupled portions of the active region ([19], Chen) and providing back-side interconnect structure for the routings for the isolation field-effect transistor device and the power circuits for other field-effect transistor devices thereby reducing the area of the resulting semiconductor structure ([32], Tsao).
Regarding claim 12, Lai in view of Chen and Tsao discloses the method of claim 11 as described above.
Lai further discloses, in at least figures 1A, 2A, 6A, 7A-7I, and related text, the FM0 interconnect layer (layer of 20F/620F/642F/644F/646F, [51]) comprises providing six or fewer parallel FM0 interconnects (20F/620F/642F/644F/646F, [51]) and wherein the BM0 interconnect layer (layer of 20B/622B/624B/642B/644B, [51]) comprises providing six or fewer parallel BM0 interconnects (20B/622B/624B/642B/644B, [51]).
Regarding claim 13, Lai in view of Chen and Tsao discloses the method of claim 11 as described above.
Lai further discloses, in at least figures 1A, 2A, 6A, 7A-7I, and related text, the FM0 interconnect layer (layer of 20F/620F/642F/644F/646F, [51]) comprises providing five or fewer parallel FM0 interconnects (20F/620F/642F/644F/646F, [51]) and wherein the BM0 interconnect layer (layer of 20B/622B/624B/642B/644B, [51]) comprises providing five or fewer parallel BM0 interconnects (20B/622B/624B/642B/644B, [51]).
Regarding claim 14, Lai in view of Chen and Tsao discloses the method of claim 11 as described above.
Lai further discloses, in at least figures 1A, 2A, 6A, 7A-7I, and related text, the FM0 interconnect layer (layer of 20F/620F/642F/644F/646F, [51]) comprises providing four or fewer parallel FM0 interconnects (20F/620F/642F/644F/646F, [51]) and wherein the BM0 interconnect layer (layer of 20B/622B/624B/642B/644B, [51]) comprises providing four or fewer parallel BM0 interconnects (20B/622B/624B/642B/644B, [51]).
Regarding claim 15, Lai in view of Chen and Tsao discloses the method of claim 11 as described above.
Lai further discloses, in at least figures 1A, 2A, 6A, 7A-7I, and related text, the FM0 interconnect layer (layer of 20F/620F/642F/644F/646F, [51]) comprises providing three or fewer parallel FM0 interconnects (20F/620F/642F/644F/646F, [51]) and wherein the BM0 interconnect layer (layer of 20B/622B/624B/642B/644B, [51]) comprises providing three or fewer parallel BM0 interconnects (20B/622B/624B/642B/644B, [51]).
Regarding claim 16, Lai in view of Chen and Tsao discloses the method of claim 11 as described above.
Lai in view of Chen does not explicitly disclose each of the first plurality of S/D structures comprises an EPI layer.
Tsao teaches, in at least figure 12 and related text, the device comprising each of the first plurality of S/D structures (240-1S1/240-1S2/240-2S1/240-2S2, [48]) comprises an EPI layer ([48]), for the purpose of eliminating substrate leakage ([48]).
Lai, Chen, and Tsao are analogous art because they all are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lai in view of Chen with the specified features of Tsao because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Lai in view of Chen to have the each of the first plurality of S/D structures comprises an EPI layer, as taught by Tsao, for the purpose of providing larger source/drain and eliminating substrate leakage ([48], Tsao).
Regarding claim 17, Lai in view of Chen and Tsao discloses the method of claim 11 as described above.
Lai in view of Tsao does not explicitly disclose the metal gate structure comprises a high-K dielectric layer at least partially surrounding a work function metal layer.
Chen teaches, in at least figure 1B and related text, the metal gate structure (151, [37]) comprises a high-K dielectric layer at least partially surrounding a work function metal layer ([37], figure), for the purpose of providing better controllability of gate for carriers in channel and tunning threshold voltage of transistor.
Lai, Chen, and Tsao are analogous art because they all are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lai in view of Tsao with the specified features of Chen because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Lai in view of Tsao to have the metal gate structure comprising a high-K dielectric layer at least partially surrounding a work function metal layer, as taught by Chen, for the purpose of providing better controllability of gate for carriers in channel and tunning threshold voltage of transistor.
Regarding claim 20, Lai in view of Chen and Tsao discloses the method of claim 11 as described above.
Lai further discloses, in at least figures 1A, 2A, 6A, 7A-7I, and related text, the plurality of gate structures (gB2/gB1/gA1/gA2, [45]) are spaced apart from each other by one of a second plurality of S/D structures (source/drain regions in 80n, [48]) offset from the first plurality of S/D structures (source/drain regions in 80p, [46]), each gate structure (gB2/gB1/gA1/gA2, [45]) comprising a second channel structure (80n, [48]) and a second gate structure (gB2/gB1/gA1/gA2, [45]), the second channel structure (gB2/gB1/gA1/gA2, [45]) comprising at least one channel connecting (80n, [48]) adjacent S/D structures in the second plurality of S/D structures (source/drain regions in 80n, [48]) to each other.
Lai in view of Tsao does not explicitly disclose each gate structure comprising a second channel structure and a second metal gate structure.
Chen further teaches, in at least figure 1B and related text, each gate structure (151, [37]) comprising a second channel structure (152, [37]) and a second metal gate structure ([37]), for the purpose of providing better controllability of gate for carriers in channels.
Lai, Chen, and Tsao are analogous art because they all are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lai in view of Tsao with the specified features of Chen because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Lai in view of Tsao to have each gate structure comprising a second channel structure and a second metal gate structure, as taught by Chen, for the purpose of providing better controllability of gate for carriers in channels.
Claim(s) 8-9 and 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lai (US 2023/0067311) in view of Chen (US 2021/0375853), Tsao (US 2023/0223276), and further in view of Liaw (US 2023/0012680).
Regarding claim 8, Lai in view of Chen and Tsao discloses the semiconductor device of claim 1 as described above.
Lai in view of Chen and Tsao does not explicitly disclose the channel structure is contained within a first portion of the metal gate structure and not within a second portion of the metal gate structure.
Liaw teaches, in at least figures 3A, 3I, and related text, the device comprising the channel structure (228, [36]) is contained within a first portion of the metal gate structure (232, [36], [99]) and not within a second portion (232 area closed to 236, [101], figure) of the metal gate structure (232, [36], [99]), for the purpose of providing an IC chip logic cells with power rail on the back side, and tap structures to connect low-voltage power lines from the back side to the front side ([20]) thereby improving density of integration.
Lai, Chen, Tsao, and Liaw are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lai in view of Chen and Tsao with the specified features of Liaw because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Lai in view of Chen and Tsao to have the channel structure being contained within a first portion of the metal gate structure and not within a second portion of the metal gate structure, as taught by Liaw, for the purpose of providing an IC chip logic cells with power rail on the back side, and tap structures to connect low-voltage power lines from the back side to the front side ([20], Liaw) thereby improving density of integration.
Regarding claim 9, Lai in view of Chen, Tsao, and Liaw discloses the semiconductor device of claim 1 as described above.
Lai in view of Chen and Tsao does not explicitly disclose the second portion of the metal gate structure is separated from the BS-ILD layer by a shallow trench isolation (STI) layer.
Liaw teaches, in at least figures 3A, 3I, 3L, and related text, the second portion (232 area closed to 236, [101], figure) of the metal gate structure (232, [36], [99]) is separated from the BS-ILD layer (216, [31]) by a shallow trench isolation (STI) layer (206, [28]), for the purpose of providing lateral isolation of gate structures and vertical isolation of gate structures from backside power lines to increase density of integration.
Lai, Chen, Tsao, and Liaw are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lai in view of Chen and Tsao with the specified features of Liaw because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Lai in view of Chen and Tsao to have the second portion of the metal gate structure being separated from the BS-ILD layer by a shallow trench isolation (STI) layer, as taught by Liaw, for the purpose of providing lateral isolation of gate structures and vertical isolation of gate structures from backside power lines to increase density of integration.
Regarding claim 18, Lai in view of Chen and Tsao discloses the method of claim 11 as described above.
Lai in view of Chen and Tsao does not explicitly disclose the channel structure is contained within a first portion of the metal gate structure and not within a second portion of the metal gate structure.
Liaw teaches, in at least figures 3A, 3I, and related text, the method comprising the channel structure (228, [36]) is contained within a first portion of the metal gate structure (232, [36], [99]) and not within a second portion (232 area closed to 236, [101], figure) of the metal gate structure (232, [36], [99]), for the purpose of providing an IC chip logic cells with power rail on the back side, and tap structures to connect low-voltage power lines from the back side to the front side ([20]) thereby improving density of integration.
Lai, Chen, Tsao, and Liaw are analogous art because they both are directed to method for forming a semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lai in view of Chen and Tsao with the specified features of Liaw because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method disclosed in Lai in view of Chen and Tsao to have the channel structure being contained within a first portion of the metal gate structure and not within a second portion of the metal gate structure, as taught by Liaw, for the purpose of providing an IC chip logic cells with power rail on the back side, and tap structures to connect low-voltage power lines from the back side to the front side ([20], Liaw) thereby improving density of integration.
Regarding claim 19, Lai in view of Chen, Tsao, and Liaw discloses the method of claim 18 as described above.
Lai in view of Chen and Tsao does not explicitly disclose the second portion of the metal gate structure is separated from the BS-ILD layer by a shallow trench isolation (STI) layer.
Liaw teaches, in at least figures 3A, 3I, 3L, and related text, the second portion (232 area closed to 236, [101], figure) of the metal gate structure (232, [36], [99]) is separated from the BS-ILD layer (216, [31]) by a shallow trench isolation (STI) layer (206, [28]), for the purpose of providing lateral isolation of gate structures and vertical isolation of gate structures from backside power lines to increase density of integration.
Lai, Chen, Tsao, and Liaw are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lai in view of Chen and Tsao with the specified features of Liaw because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Lai in view of Chen and Tsao to have the second portion of the metal gate structure being separated from the BS-ILD layer by a shallow trench isolation (STI) layer, as taught by Liaw, for the purpose of providing lateral isolation of gate structures and vertical isolation of gate structures from backside power lines to increase density of integration.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONG-HO KIM whose telephone number is (571)270-0276. The examiner can normally be reached Monday thru Friday; 8:30 AM to 5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TONG-HO KIM/Primary Examiner, Art Unit 2811