DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-19 and 24 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by SONG et al. (US 20190268000 A1, hereinafter Song)
With regards to claim 1, Song discloses an integrated circuit comprising:
a first cell (logic cells LC1) in a first row extending in a first direction;
a first power line (IL VDD) extending in the first direction in a power rail layer, and configured to provide a first supply voltage to the first cell; (See FIG. 19) and
a first pattern (leftmost active contact AC of FIG. 19) overlapping a first boundary of the first row, and extending in the first direction in a first wiring layer,
wherein the first cell includes:
at least one pattern (VI interconnect layer IL) extending in the first direction in the first wiring layer; and
at least one transistor (transistor comprising gate electrode GE connected to VI IL) between the power rail layer and the first wiring layer,
wherein the first pattern is configured to receive a first input signal or a first output signal of the first cell. (see FIG. 19, showing the configuration for receiving a signal)
With regards to claim 2, Song discloses the integrated circuit of claim 1, further comprising:
a second pattern (middle active contacts AC of FIG. 19) electrically connected to the first pattern, and extending in a second wiring layer in a second direction that is perpendicular to the first direction. (see FIG. 19)
With regards to claim 3, Song discloses the integrated circuit of claim 1, further comprising:
a second cell (logic cells LC2) in the first row, and including one or more patterns extending in the first direction in the first wiring layer,
wherein the first pattern overlaps a boundary of the second cell and is electrically insulated from the second cell. (see FIG. 19, showing the overlap from left to right)
With regards to claim 4, Song discloses the integrated circuit of claim 1, further comprising:
a second cell (logic cells LC2) in the first row or a second row adjacent to the first row, and including one or more patterns (active contacts AC) extending in the first direction in the first wiring layer,
wherein the first pattern is configured to receive a second input signal or a second output signal of the second cell. (see FIG. 19, showing the configuration for receiving a signal)
With regards to claim 5, Song discloses the integrated circuit of claim 4, wherein each of the first cell and the second cell is configured to receive a clock signal as the first or second input signal, and the first pattern is configured to receive the clock signal. (VDD, see FIG. 19, showing the configuration for receiving a signal)
With regards to claim 6, Song discloses the integrated circuit of claim 4, wherein the first row has a first height that is different from a second height of the second row. (See Fig 19, showing the different heights of different rows)
With regards to claim 7, Song discloses the integrated circuit of claim 1, further comprising:
a second pattern (C shaped interconnect layer IL) overlapping a second boundary of the first row, and extending in the first direction in the first wiring layer.
With regards to claim 8, Song discloses the integrated circuit of claim 1, further comprising:
a second power line (IL VSS) extending in the first direction in the power rail layer, and configured to provide a second supply voltage to the first cell. (See FIG. 19)
With regards to claim 9, Song discloses the integrated circuit of claim 1, wherein the at least one pattern and the first pattern overlap tracks extending in the first direction and at a uniform pitch in a second direction that is perpendicular to the first direction. (See FIG. 19, showing the overlap from left to right of the Figure)
With regards to claim 10, Song discloses the integrated circuit of claim 1, wherein the first pattern has a width that is same as a width of each of the at least one pattern in a second direction that is perpendicular to the first direction. (See FIG. 19, wherein the patterns have at least one same width)
With regards to claim 11, Song discloses the integrated circuit of claim 1, wherein the first cell comprises:
at least one first via (via VI) electrically connected to the at least one pattern; and
at least one second via (via directly connected to active pattern AC, see FIG. 19) electrically connected to the first power line.
With regards to claim 12, Song discloses an integrated circuit comprising:
a first cell (logic cells LC1) in a first row extending in a first direction;
a first power line (IL VDD) extending in the first direction in a power rail layer, and configured to provide a first supply voltage to the first cell; and
a first pattern (leftmost active contact AC of FIG. 19) and a second pattern (adjacent active contact AC of FIG. 19) adjacent to each other, and each extending in the first direction in a first wiring layer, a first boundary between the first row and a second row adjacent to the first row being between the first pattern and the second pattern, wherein the first cell includes:
at least one pattern (active contacts AC) extending in the first direction in the first wiring layer; and
at least one transistor (transistor comprising gate electrode GE) between the power rail layer and the first wiring layer, wherein the first pattern is configured to receive a first input signal or a first output signal of the first cell. (see FIG. 19, showing the configuration for receiving a signal)
With regards to claim 13, Song discloses the integrated circuit of claim 12, further comprising:
a second cell (logic cells LC2) arranged in the second row, and including one or more patterns (middle active contacts AC of FIG. 19) extending in the first direction in the first wiring layer, wherein the second pattern is configured to receive a second input signal or a second output signal of the second cell. (see FIG. 19, showing the configuration for receiving a signal)
With regards to claim 14, Song discloses the integrated circuit of claim 12, further comprising:
a third pattern (right middle active contacts AC of FIG. 19) electrically connected to the first pattern, and extending in a second wiring layer (gate electrode GE) in a second direction that is perpendicular to the first direction. (see FIG. 19)
With regards to claim 15, Song discloses the integrated circuit of claim 12, further comprising:
a second cell (logic cells LC2) in the first row, and including one or more patterns extending in the first direction in the first wiring layer, wherein the first pattern overlaps a boundary of the second cell, and is electrically insulated from the second cell. (See FIG. 19)
With regards to claim 16, Song discloses the integrated circuit of claim 12, further comprising:
a second cell (logic cells LC2) in the first row or the second row, and including one or more patterns (active contacts AC of FIG. 19) extending in the first direction in the first wiring layer, wherein the first pattern is configured to receive a second input signal or a second output signal of the second cell. (see FIG. 19, showing the configuration for receiving a signal)
With regards to claim 17, Song discloses the integrated circuit of claim 16, wherein each of the first cell and the second cell is configured to receive a clock signal (VDD) as the first or second input signal, and the first pattern is configured to receive the clock signal. (See Fig 19)
With regards to claim 18, Song discloses the integrated circuit of claim 12, wherein the first row has a first height that is different from a second height of the second row. (See Fig 19, showing the different heights of different rows))
With regards to claim 19, Song discloses the integrated circuit of claim 12, further comprising:
a third pattern (right middle active contacts AC of FIG. 19) adjacent to a second boundary of the first row, and extending in the first direction in the first wiring layer. (See Fig 19)
With regards to claim 24, Song discloses an integrated circuit comprising:
a plurality of cells (logic cells LC1-LC3) in a plurality of rows extending in a first direction;
a plurality of power lines (IL VDD) extending in the first direction in a power rail layer, and configured to provide a first supply voltage or a second supply voltage to each of the plurality of cells; and
a plurality of first patterns (active contacts AC) overlapping respective boundaries of the plurality of rows or immediately adjacent to the respective boundaries, (separation structures DB1) and extending in the first direction in a first wiring layer, (IL VSS) wherein each of the plurality of cells includes:
at least one second pattern (C-shaped interconnect line IL) extending in the first direction in the first wiring layer; and
at least one transistor (transistor comprising gate electrode GE) between the power rail layer and the first wiring layer,
wherein the plurality of first patterns include a first pattern configured to receive a first input signal or a first output signal of a first cell among the plurality of cells in a first row among the plurality of rows. (see FIG. 19, showing the configuration for receiving a signal)
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Fan et al. (US 20170154848 A1) – power structure with vias shown in a plan view.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN M Page whose telephone number is (571)272-3249. The examiner can normally be reached M-F: 10:00AM-6:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8548. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STEVEN M PAGE/Primary Patent Examiner, Art Unit 2812