DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to applicant’s Election/Restriction filed on 02/02/2026.
Currently claims 1-18 are pending in the application.
Election/Restrictions
Applicant's election without traverse of Species B, claims 11-18, in the reply filed on 02/02/2026 is acknowledged.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 09/19/2023 and 03/21/2025 were filed before the mailing date of the office action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements were considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim 11 is rejected under 35 U.S.C. 102 (a) (1) as being anticipated by US 2019/0096791 A1 (Jeng).
Regarding claim 11, Jeng discloses, a power module (Fig. 1E; [0014] – [0037]), comprising:
PNG
media_image1.png
492
722
media_image1.png
Greyscale
a device substrate (as annotated on Fig. 1E, rectangular box) having a first surface and a second surface opposite to the first surface (as annotated on Fig. 1E; [0019] – [0024]);
the device substrate comprises:
at least one power device chip (100a, as annotated on Fig. 1E; [0020]) embedded within the device substrate (Fig. 1E; [0019] – [0024]); and
at least one pair of connecting pillars (TIV, as annotated on Fig. 1E; [0019]) embedded within the device substrate, and wherein the at least one pair of connecting pillars (TIV) comprises a first connecting pillar (left) and a second connecting pillar (right) arranged at opposite sides of the at least one power device chip (100a);
wherein the at least one power device chip (100a) has a first surface (top surface) covered by a top heat layer (100d; heat dissipation layer; Fig. 1E; [0020]) exposed on the first surface (exposed on the top surface through the intervening encapsulation layer E) of the device substrate, and a second surface (bottom surface) comprises a plurality of pins (as annotated on Fig. 1E) exposed on the second surface of the device substrate (Fig. 1E; [0016]), and wherein the first surface and the second surface of the at least one power device chip are opposite (as evident in Fig. 1E).
Regarding claim 12, Jeng discloses, the power module of claim 11, further comprising a bottom substrate (102; redistribution layer structure; Fig. 1E; [0016]) having a first surface (top surface) attached to the second surface of the device substrate (as annotated on Fig. 1E, rectangular box) and a second surface (bottom surface) having a plurality of pads (103; redistribution layers; as annotated on Fig. 1E; [0016]),
PNG
media_image2.png
492
722
media_image2.png
Greyscale
wherein the first surface and the second surface of the bottom substrate (102) are opposite (as evident in Fig. 1E), and
wherein some of the plurality of pins (as annotated on Fig. 1E) of the at least one power device chip (100a) are electrically connected to some of the plurality of pads (103) on the second surface of the bottom substrate (102) respectively (as evident in Fig. 1E).
Allowable Subject Matter
Claims 13-18 are objected to as being dependent upon rejected base claims, but would be allowable if rewritten in independent forms including all of the limitations of the base claims and any intervening claims.
Regarding claim 13, the closest prior art, US 2019/0096791 A1 (Jeng), fails to disclose, “the power module of claim 12, wherein the at least one power device chip comprises:
an input pin;
a switching pin;
a ground pin;
a driving pin;
a first switch having a first terminal coupled to the input pin, a second terminal coupled to the switching pin, and a control terminal configured to receive a first driving signal;
a second switch having a first terminal coupled to the switching pin, a second terminal coupled to the ground pin, and a control terminal configured to receive a second driving signal; and
a driver coupled to the driving pin to receive a phase control signal, and to provide the first driving signal and the second driving signal based on the phase control signal;
wherein the plurality of pads on the second surface of the bottom substrate are zoned into an input pad area, a ground pad area, a signal pad area, a first output voltage pad area and a second output voltage pad area, and wherein each one of the input pad area, the ground pad area, the signal pad area, the first output voltage pad area and the second output voltage pad area comprises at least one pad;
the input pin of the at least one power device chip is electrically connected to the at least one pad of the input pad area on the second surface of the bottom substrate;
the ground pin of the at least one power device chip is electrically connected to the at least one pad of the ground pad area on the second surface of the bottom substrate; and
the driving pin of the at least one power device chip is electrically connected to the at least one pad of the signal pad area on the second surface of the bottom substrate”, in combination with the additionally claimed features, as are claimed by the Applicant.
Regarding claim 14, the closest prior art, US 2019/0096791 A1 (Jeng), fails to disclose, “the power module of claim 12, further comprising an inductor assembly arranged on the device substrate,
wherein the inductor assembly comprises:
a magnetic core having a first surface and a second surface opposite to the first surface of the magnetic core; and
at least one winding passing through the magnetic core, wherein the at least one winding has a first portion, a second portion and a middle portion connecting the first portion and the second portion, and
wherein the first portion and the second portion of the at least one winding is vertical to the first surface of the magnetic core, and
a middle portion of the at least one winding is parallel to the first surface of the magnetic core, and
wherein the first portion and the second portion of the at least one winding respectively has an end connected out of the second surface of the magnetic core”, in combination with the additionally claimed features, as are claimed by the Applicant.
Claims 15-18 are also objected to due to their dependence on an objected base claim.
Examiner’s Note (Additional Prior Arts)
The examiner included a few prior arts which were not used in the rejection but are relevant to the disclosure.
US 2021/0118805 A1 (Sio) - A semiconductor structure is disclosed having a power distribution network including first and second conductive lines. A substrate includes a first surface that is in contact with the power distribution network. A plurality of backside vias are in the substrate and electrically coupled to the first conductive line. A via rail is on a second surface of the substrate that opposes the first surface. A first interlayer dielectric is on the via rail and on the substrate. A second interlayer dielectric is on the first interlayer dielectric. A third interlayer dielectric is on the second interlayer dielectric. First and top interconnect layers are in the second and third interlayer dielectrics, respectively. Deep vias are in the third interlayer dielectric and electrically coupled to the via rail. The deep vias are also connected to the first and top interconnect layers. A power supply in/out layer is on the third interlayer dielectric and in contact with the top interconnect layer.
US 2020/0020635 A1 (Chang) – A semiconductor structure is disclosed including a first chip with a first conductive line and a first conductive island formed on the first conductive line. The first chip also includes a first plurality of vias formed in the first conductive island and electrically coupled to the first conductive line. The semiconductor structure further includes a second chip bonded to the first chip, where the second chip includes a second conductive line and a second conductive island formed on the second conductive line. The second chip also includes a second plurality of vias formed in the second conductive island and electrically coupled to the second conductive line.
US 2019/0109538 A1A1 (Zhou) - A circuit assembly for a power converter is disclosed including power stage blocks. A power stage block includes a power stage IC die, an output inductor that is connected to a switch node of the power stage IC die, and capacitors that form an output capacitor of the power stage block. The output capacitors of the power stage blocks are symmetrically arranged. The output inductors can be placed on the same side of the substrate as the power stage IC dies, or on a side of the substrate that is opposite to the side where the power stage IC dies are disposed. A power stage block may generate two output phases of the power converter.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to S M SOHEL IMTIAZ whose telephone number is (408) 918-7566. The examiner can normally be reached on 8AM-5PM, M-F, PST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/S M SOHEL IMTIAZ/Primary Patent Examiner
Art Unit 2812
02/20/2026