DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In response to an Office action mailed on 02/18/2026 (“02/18/2026 OA”), the Applicant amended independent claim 1 and claim 5 in a reply filed on 05/12/2026. Applicant’s amendments to independent claim 1 have substantively changed the scope of claim 1 and its dependent claims.
Claims 11-20 are withdrawn.
Currently, claims 1-10 are examined as below.
Response to Arguments
Applicant’s amendments to independent claim 1 have overcome the prior-art rejections as set forth under line item numbers 1-3 in the 02/18/2026 OA.
I. Prior-art rejections based on He and Vedula
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 and 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over US 2006/0024905 A1 to He et al. (“He”) in view of US 2019/0109570 A1 to Vedula et al. (“Vedula”).
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Regarding independent claim 1, He in Figs. 1A-1E teaches an integrated circuit (IC) Figs. 1A-1E, ¶ 24, ¶ 27, ¶ 32 & ¶ 34, integrated circuit includes MOS capacitor comprising substrate 100, gate conductor 200 and dielectric 300, and a metal interconnect capacitor comprising metal levels M1-M5), comprising:
a metal-oxide-metal (MOM) capacitor (MOMCAP) M1-M5/304 (Figs. 1A-1E & ¶ 34, a collective of metal interconnect capacitor M1-M5 and dielectric 304 between the metal levels M1-M5), comprising:
a first terminal 414 (Figs. 1B, 1D & ¶ 34, metal contact bus 414) coupled to a first plurality of fingers 415 (Figs. 1A-1D & ¶ 34, metal fingers 415) of a first metal interconnect layer M1 (Figs. 1A-1D & ¶ 34, metal level M1), and
a second terminal 410 (Figs. 1B, 1D & ¶ 34, metal contact bus 410) coupled to a second plurality of fingers 411 (Figs. 1B, 1D & ¶ 34, metal fingers 411) of the first metal interconnect layer M1 and interdigitated with the first plurality of fingers 415 of the first metal interconnect layer (Fig. 1D & ¶ 35-¶ 36); and
a first metal-oxide-semiconductor (MOS) capacitor (MOSCAP) 100/200/300 (Figs. 1A-1C & ¶ 27, a collective of substrate 100, gate conductor 200 and dielectric 300) beneath the first metal interconnect layer M1 (Figs. 1A-1B) and comprising:
a polysilicon terminal 200 (Figs. 1A-1C, ¶ 27 & ¶ 32, gate conductor 200 comprises polysilicon) on an oxide 300 (Figs. 1A-1B, ¶ 32, dielectric 300 comprising silicon dioxide) of an N-type well (N-well) 110 (Figs. 1A-1B, ¶ 27, n-doped region 110 i.e., N-type well) of a substrate 100 (Figs. 1A-1B, ¶ 11, ¶ 27, substrate 100 is a semiconductor substrate) and coupled to the first plurality of fingers 415 of the MOMCAP M1-M5/304 through a first interlayer dielectric (ILD) 304 (Figs. 1A-1B, ¶ 34, dielectric 304 fills between the layers 415 of the metal levels M1-M5, and is therefore an interlayer dielectric; Figs. 1A-1B, the terminal 200 connects together with (i.e., couples to) the fingers 415 through the dielectric 304), and
a diffusion terminal 120 (Fig. 1A, ¶ 27, a collective of highly n-doped source/drain regions 120) provided by diffusion regions 120 (Fig. 1A, ¶ 27, highly n-doped source/drain regions 120) and coupled to the second plurality of fingers 411 of the MOMCAP M1-M5/304 through the first ILD 304 (Figs. 1A, 1D, the terminal 120 connects together with (i.e., couples to) the fingers 411 through the dielectric 304).
However, He does not explicitly disclose the substrate is a semiconductor-on-insulator (SOI) substrate.
Vedula recognizes a need for reducing parasitic device capacitance and improving performance of a device (¶ 20). Vedula satisfies the need by providing a semiconductor on insulator (SOI) substrate for a device substrate (¶ 20).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify the substrate taught by He with the SOI substrate taught by Vedula, so as to reduce parasitic device capacitance and improve performance of a device (Vedula: ¶ 20).
Regarding claim 3, He in Figs. 1B-1D further teaches the diffusion terminal 110 is coupled to the second terminal 410 through a plurality of diffusion contacts 500 (Figs. 1B-1D & ¶ 42, vertical contacts 500 that connect to the diffusion terminal 110 make the contacts 500 diffusion contacts).
Regarding claim 4, He in Figs. 1B-1D further teaches the diffusion terminal 110 is coupled to ends of the second plurality of fingers 411 (Figs. 1C-1D, the diffusion terminal 110 couples to ends of fingers 411 through vertical contacts 500 and metal contact bus 410), distal from the second terminal 410 through a plurality of diffusion contacts 500 (Fig. 1B & ¶ 42, the diffusion terminal 110 is distal from the terminal 410 through contacts 500).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over He and Vedula, and further in view of US 11,121,072 B1 to Zhu et al. (“Zhu”).
Regarding claim 2, He in Figs. 1A-1D teaches outer ones of the first plurality of fingers 415 are coupled to the polysilicon terminal 200 through a plurality of contacts 520 (Fig. 1B & ¶ 42, vertical contacts 520).
He further discloses the contacts 520 are vertical contacts (Fig. 1B & ¶ 42).
However, the combination of He and Vedula does not explicitly disclose the vertical contacts are polysilicon contacts.
Zhu recognizes a need for providing an interconnect structure that electrically couples different components (col. 5, ln. 27-52). Zhu satisfies the need by providing vertical contacts 46, 48, 50 (Fig. 2 & col. 5, ln. 27-52, fingers 46, 48, 50) that are polysilicon contacts (col. 5, ln. 27-52).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to use polysilicon taught by Zhu for the vertical contacts taught by He and Vedula, so as to provide an interconnect structure that electrically couples different components (Zhu: col. 5, ln. 27-52).
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over He and Vedula, and further in view of US 2019/0386092 A1 to Cheng et al. (“Cheng”).
Regarding claim 9, the combination of He and Vedula does not explicitly disclose the IC of claim 1 integrated in a radio frequency (RF) front-end (RFFE) module.
He further discloses the IC comprises the MOM capacitor M1-M5/304 and the MOS capacitor 100/200/300.
Cheng recognizes a need for improving analog/radio frequency (RF) performance and supporting communication enhancements (¶ 2). Cheng satisfies the need by integrating high performance capacitor components including a MOM capacitor and a MOS capacitor to a radio frequency front end (RFFE) module (¶ 2-¶ 3 & ¶ 35-¶ 39).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to combine the IC taught by He and Vedula with the RFFE module taught by Cheng, so as to improve analog/radio frequency (RF) performance and support communication enhancements (Cheng: ¶ 2).
Regarding claim 10, the combination of He, Vedula and Cheng further teaches the RFFE module is integrated in a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit, and/or a fixed location data unit (Cheng: ¶ 107).
II. Prior-art rejections based on He and Chen
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over He in view of US 2011/0193658 A1 to Chen et al. (“Chen”).
Regarding independent claim 1, He in Figs. 1A-1E teaches an integrated circuit (IC) Figs. 1A-1E, ¶ 24, ¶ 27, ¶ 32 & ¶ 34, integrated circuit includes MOS capacitor comprising substrate 100, gate conductor 200 and dielectric 300, and a metal interconnect capacitor comprising metal levels M1-M5), comprising:
a metal-oxide-metal (MOM) capacitor (MOMCAP) M1-M5/304 (Figs. 1A-1E & ¶ 34, a collective of metal interconnect capacitor M1-M5 and dielectric 304 between the metal levels M1-M5), comprising:
a first terminal 414 (Figs. 1B, 1D & ¶ 34, metal contact bus 414) coupled to a first plurality of fingers 415 (Figs. 1A-1D & ¶ 34, metal fingers 415) of a first metal interconnect layer M1 (Figs. 1A-1D & ¶ 34, metal level M1), and
a second terminal 410 (Figs. 1B, 1D & ¶ 34, metal contact bus 410) coupled to a second plurality of fingers 411 (Figs. 1B, 1D & ¶ 34, metal fingers 411) of the first metal interconnect layer M1 and interdigitated with the first plurality of fingers 415 of the first metal interconnect layer (Fig. 1D & ¶ 35-¶ 36); and
a first metal-oxide-semiconductor (MOS) capacitor (MOSCAP) 100/200/300 (Figs. 1A-1C & ¶ 27, a collective of substrate 100, gate conductor 200 and dielectric 300) beneath the first metal interconnect layer M1 (Figs. 1A-1B) and comprising:
a polysilicon terminal 200 (Figs. 1A-1C, ¶ 27 & ¶ 32, gate conductor 200 comprises polysilicon) on an oxide 300 (Figs. 1A-1B, ¶ 32, dielectric 300 comprising silicon dioxide) a substrate 100 (Figs. 1A-1B, ¶ 11, ¶ 27, substrate 100 is a semiconductor substrate) and coupled to the first plurality of fingers 415 of the MOMCAP M1-M5/304 through a first interlayer dielectric (ILD) 304 (Figs. 1A-1B, ¶ 34, dielectric 304 fills between the layers 415 of the metal levels M1-M5, and is therefore an interlayer dielectric; Figs. 1A-1B, the terminal 200 connects together with (i.e., couples to) the fingers 415 through the dielectric 304), and
a diffusion terminal 120 (Fig. 1A, ¶ 27, a collective of highly n-doped source/drain regions 120) provided by diffusion regions 120 (Fig. 1A, ¶ 27, highly n-doped source/drain regions 120) and coupled to the second plurality of fingers 411 of the MOMCAP M1-M5/304 through the first ILD 304 (Figs. 1A, 1D, the terminal 120 connects together with (i.e., couples to) the fingers 411 through the dielectric 304).
However, He does not explicitly disclose the substrate is a semiconductor-on-insulator (SOI) substrate having an N-type well (N-well).
Chen recognizes a need for improving coupling effects between components above a substrate in a device (¶ 15). Chen satisfies the need by providing a semiconductor-on-insulator (SOI) substrate 165 (Fig. 2, ¶ 14, ¶ 20, silicon-on-insulator (SOI) substrate 165) having an N-type well (N-well) 215 (Fig. 2, ¶ 20, N-well section 215) for a device.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify the substrate taught by He with the SOI substrate having the N-well taught by Chen, so as to improve coupling effects between components above a substrate in a device (Chen: ¶ 15).
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Claims 5-8 are allowed.
Independent claim 5 is allowed, because claim 5 has been rewritten in independent form to include all of the limitations of the base claim and any intervening claims as set forth under line item number 4 in the 02/18/2026 OA.
Claims 6-8 are allowed, because they depend from the allowed claim 5.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIKKA LIU whose telephone number is (571)272-2568. The examiner can normally be reached on 9AM-5AM EST M-F.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached on 571-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/M.L./Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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