DETAILED ACTION
The Amendment filed April 03, 2026 has been entered. Claims 1-30 are pending. Claims 15-25 and 28-30 are withdrawn from consideration as being drawn to non-elected inventions without traverse. Claims 1, 11 and 26 are independent.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 9 and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Patel et al. (US 2015/0348594).
Regarding independent claim 1 and its method independent claim 11, Patel et al. disclose a memory (see e.g., FIG. 1 along with EXMINER’S MARKUP below) comprising:
a first bank (102-3) of bitcells arranged into a first plurality of columns;
a first plurality of read column multiplexers (104-2; and para. 0011: … directs read/write operations … a column multiplexer (MUX) …) coupled to the first bank of bitcells arranged into the first plurality of columns, the first plurality of read column multiplexers being located adjacent a first edge of the first bank of bitcells (see EXMINER’S MARKUP below);
a second bank (102-2) of bitcells arranged into a second plurality of columns, wherein a first edge of the second bank of bitcells is positioned to face the first edge of the first bank of bitcells (see EXMINER’S MARKUP below);
a second plurality of read column multiplexers (104-1) coupled to the second bank of bitcells arranged into the second plurality of columns, the second plurality of read column multiplexers being located adjacent to the first edge of the second bank of bitcells (see EXMINER’S MARKUP below);
a plurality of read circuits (101; and para. 0017: the global I/O module 101 via the read global bitline pair 111) being located adjacent to a second edge of the second bank of bitcells (see EXMINER’S MARKUP below); and
a first plurality of read bit lines (see BL/BLB though GBL/GBLB) coupled to the first plurality of read column multiplexers (104-2), the second plurality of read column multiplexers (104-1), and a plurality of sense amplifiers (FIG. 3: 310-320).
Further, regarding method claim 11, MPEP 2112.02(I) instructs examiners, “Under the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device will inherently perform the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed. Cir. 1986).” Here, the applied prior art product is identical to applicant’s disclosed product, and therefore is assumed, in accordance with MPEP 2112.02(I), to inherently perform the claimed process.
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Regarding claim 2, which depends from claim 1, Patel et al. disclose the read column multiplexers from the first plurality of read column multiplexers and from the second plurality of read column multiplexers are arranged into pairs of read column multiplexers, each pair of read column multiplexers including a corresponding read column multiplexer from the first plurality of read column multiplexers and a corresponding read column multiplexer from the second plurality of read column multiplexers, and wherein each pair of read column multiplexers couples to a pair of output nodes (FIGS. 1-2 and accompanying disclosure).
Regarding claims 3-4, which depends from claim 2, Patel et al. disclose the first plurality of read bit lines are arranged into pairs to form pairs of read bit lines, and wherein each pair of read bit lines is coupled to a corresponding pair of output nodes; and each pair of read bit lines comprises a read bit line and a complement read bit line and each pair of output nodes comprises a positive output node and a complement output node, and wherein each read bit line is coupled to a corresponding positive output node and each complement read bit line is coupled to a corresponding complement output node (FIGS. 1-3 and accompanying disclosure).
Regarding claim 9, which depends from claim 1, Patel et al. disclose the memory comprises a static random- access memory (para. 0021: SRAM).
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-6, 8, 10 and 14 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Patel et al. (US 2015/0348594).
Regarding claims 5-6, Patel et al. teach the limitations of claim 2.
Patel et al. further teach a plurality of local bit lines for the first bank of bitcells and for the second bank of bitcells are disposed within a first metal layer (see FIGS. 1-3: metal layers) adjacent a semiconductor substrate; and the first plurality of read bit lines are disposed within a second metal layer adjacent the first metal layer, the first metal layer is located between the semiconductor substrate and the second metal layer, and the first plurality of read bit lines are configured to extend across the second bank of bitcells from the first edge of the second bank of bitcells to the second edge of the second bank of bitcells (FIGS. 1-3, and accompanying disclosure).
Patel et al. do not explicitly disclose routed metal layers associated with the substrate.
However, metal layers associated with the semiconductor substrate is a well-known technology for a type of semiconductor manufacturing for its purpose.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize semiconductor metal layers related to the substrate because these conventional technology are well established in the art of the memory devices.
Regarding claim 8, Patel et al. teach the limitations of claim 1.
Patel et al. further teach a plurality of data output latches coupled to the plurality of sense amplifiers (FIG. 3).
Patel et al. do not explicitly disclose data output latches.
However, latch type sense amplifier is a well-known technology in a memory device.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize sense amplifier with data latching because these conventional technology are well established in the art of the memory devices.
Regarding claim 10, Patel et al. teach the limitations of claim 1.
Patel et al. do not explicitly disclose the memory is incorporated into a cellular telephone.
However, the clamed limitation is a well-known technology in a memory device.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize semiconductor memory incorporated into a mobile device because these conventional technology are well established in the art of the memory devices.
Regarding claim 14, Patel et al. teach the limitations of claim 11.
Patel et al. do not explicitly disclose coupling a pair of local bit lines from a second selected column of bitcells from the first bank of bitcells through a third read column multiplexer to a second pair of read bit lines during the first read operation, wherein the second pair of read bit lines extend from the third read column multiplexer and across the second bank of bitcells to a second sense amplifier positioned adjacent the first sense amplifier; and sensing a third bit in the second sense amplifier during the first read operation.
However, the claimed limitations of sense amplifiers positioned for read multiplexer is a well-known technology for a type of memory for its purpose.
For support, of the above asserted facts, see for example, Nguyen et al. (US 2024/0339136), e.g., FIG. 8 and accompanying disclosure, i.e., SA 809 for banks 801 and 803 and SA 810 for banks 802 and 804.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize column selection and sense amplifier for data read operation because these conventional technology are well established in the art of the memory devices.
Claims 7 and 12-13 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Patel et al. (US 2015/0348594) in view of Gupta et al. (US 2021/0110867).
Regarding claims 7 and 12-13 Patel et al. teach the limitations of claims 1 and 11, respectively.
Patel et al. further teach the read circuits comprise a plurality of sense amplifiers, the memory further comprising: a third bank of bitcells arranged into a third plurality of columns, each column in the third bank extending from a first edge of the third bank of bitcells to a second edge of the third bank of bitcells; a third plurality of read column multiplexers coupled to the third plurality of columns, the third plurality of read column multiplexers being positioned adjacent the first edge of the third bank of bitcells; a fourth bank of bitcells arranged into a fourth plurality of columns, wherein a first edge of the fourth bank of bitcells faces the first edge of the third bank of bitcells; a fourth plurality of read column multiplexers coupled to the fourth plurality of columns, the fourth plurality of read column multiplexers being positioned adjacent the first edge of the fourth bank of bitcells; and a second plurality of read bit lines coupled to the third plurality of read column multiplexers, the fourth plurality of read column multiplexers, and the plurality of sense amplifiers (FIGS. 1-2 and accompanying disclosure).
Patel et al. do not explicitly disclose the third and fourth banks of bitcells claimed.
Gupta et al. teach the deficiencies in e.g., FIG. 1 and accompanying disclosure, i.e., first to fourth banks of bitcells having read column multiplexers and a plurality of read circuits (claimed sense amplifiers).
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Gupta et al. to the teaching of Patel et al. such that a memory, as taught by Patel et al., utilizes a plurality of memory banks, as taught by Gupta et al., for the purpose of implementing memory arrays such as Quad Core Array (Gupta, figure 1), thereby improving the capacity of memory arrays.
Claims 26-27 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Patel et al. (US 2015/0348594) in view of Song et al. (US 9,165,619).
Regarding independent claim 26, Patel et al. teach a memory comprising:
a first pair of banks (FIG. 1: 102-1 and 102-2);
a second pair of banks (102-3 and 102-4);
a sense amplifier (FIGS. 1 and 3: 103) located between the first pair of banks and the second pair of banks.
Patel et al do not explicitly disclose claimed limitations of column multiplexers.
Song et al. teach a first read column multiplexer (FIG. 3: 310) configured to couple a pair of local bit lines for an addressed column of bitcells from a first bank in the first pair of banks to a first pair of output nodes (BL-JM1 through BL-JMQ);
a second read column multiplexer (320) configured to couple a pair of local bit lines for an addressed column of bitcells from a second bank in the first pair of banks to the first pair of output nodes (BL-KM1 through BL-KMQ); and
a first pair of read bit lines coupled between the first pair of output nodes (input nodes of 330) and the sense amplifier (330 and 340 (see FIG. 1B: 150 and tri-state inverter, i.e., data sensing components)).
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Song et al. to the teaching of Patel et al. such that a memory, as taught by Patel et al., utilizes a plurality of memory banks, as taught by Song et al., for the purpose of implementing multiple memory arrays, thereby improving the capacity of memory arrays.
Regarding claim 27, Patel et al. and Song et al., as combined, teach the limitation of claim 26.
Song et al. further teach a third read column multiplexer configured to couple a pair of local bit lines for an addressed column of bitcells from a third bank in the second pair of banks to a second pair of output nodes; a fourth read column multiplexer configured to couple a pair of local bit lines for an addressed column of bitcells from a fourth bank in the second pair of banks to the second pair of output nodes; and a second pair of read bit lines coupled between the second pair of output nodes and the sense amplifier (see FIG. 2 along with FIGS. 3-6, and accompanying disclosure).
It would have been obvious to one of ordinary skill in the art before the effective filing date to further modify the invention of Song et al. for the same purpose of implementing multiple memory arrays, thereby improving the capacity of memory arrays.
Response to Argument
Applicant’s arguments filed 04/03/2026, with respect to the rejection(s) of claims under 35 USC 102 and 103, have been fully considered but are not persuasive.
For a compact prosecution, the examiner points out and answers the main features of the applicant’s argument.
Applicant argues that Patel’s multiplexers are centered in the column direction of the memory array and positioned at respective facing bank edges. The Offices’ mapping is being interpreted too broadly.
In response to the applicant’s argument, the scope of the claims is broad. The examiner examiners the claimed limitations. The applicant claimed “located adjacent the edge of the bank” and “bank is positioned to face the edge of bank”. The elements of the claim read on Patel’s figure 1. See the art rejection above for more details.
Applicant argues that Patel’s multiplexers are not dedicated to or structurally characterized as, read column multiplexers.
In response to the applicant’s argument, as the applicant’s acknowledged, Patel’s multiplexers are used for memory read/write operations. The applicant’s claims are open-ended and does not claim read-specific multiplexers.
Applicant argues that Patel’s read circuits does not locate adjacent to a second edge of the second bank.
In response to the applicant’s argument, the examiner fixed typo. See the art rejection above, including the aforementioned EXMINER’S MAKUP.
Applicant argues that Patel does not disclose a single plurality of read bit lines coupled to both read multiplexers and sense amplifiers.
In response to the applicant’s argument, the examiner examines the claimed limitations. The claimed “a first plurality of read bit line” electrically coupled local bit lines, global bit lines and sense amplifiers. See the mapping of the art rejection above for more details.
Applicant argues that Patel does not disclose the recited facing-bank architecture with facing multiplexer placement.
In response to the applicant’s argument, the applicant claimed “facing”. Based on broadest and reasonable interpretation, one of the meanings of “face” is “to have the front oriented toward” (Merriam-Webster Dictionary). See the art rejection above, including the aforementioned EXMINER’S MAKUP.
Applicant argues that method claims are not anticipated unless the prior art necessarily performs the claimed steps.
In response to the applicant’s arguments, regarding method claim(s), where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. Examiner has an authority to shift the burden to applicant and require applicant to either: (1) show the prior art memory device and the claimed memory device are not substantially identical; or (2) prove, by evidence, that the prior art memory device is not capable of performing the functions claimed. see MPEP 2112.01(I).
Therefore, it is respectfully submitted that the examiner maintains the rejection.
For a compact prosecution, the examiner includes prior art that was reviewed but not cited as a basis for the grounds of rejection.
Verma et al. (US 2020/0327932), figures 2 and 4, and accompanying disclosure.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUNG IL CHO whose telephone number is (571)270-0137. The examiner can normally be reached on M-Th, 7:30AM-5PM; Every other F, 7:30AM-4PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander G Sofocleous can be reached on 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SUNG IL CHO/ Primary Examiner, Art Unit 2825
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