DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of group 1, claims 1-16 in the reply filed on 2/10/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 9/19/2023 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The abstract and title are consistent with the requirements set forth in the MPEP 608.01(b) and 606, respectively.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 10 and 12 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chen et al. US PGPub. 2024/0071982. Regarding claim 1, Chen teaches a method (fig. 3-10) of manufacturing a semiconductor package (300, fig. 10) [0038], the method comprising: applying a plurality of forces (second downward force of 20N-50N, [0032]; hereinafter called FA and FB, see explanation below) to a plurality of points (areas corresponding with 252A and 252B, fig. 7A; hereinafter called 252A’ for the center of the chip and 252B’ for the edge of the chip) of a semiconductor chip (202, fig. 7A) [0032] through a plurality of elastic members (252A and 252B, fig. 7A) [0032]; and bonding [0032] the semiconductor chip (202) to an object (230, fig. 7A) [0032] while the plurality of forces (FA and FB) are applied to the plurality of points (252A’ and 252B’) of the semiconductor chip (202) through the plurality of elastic members (252A and 252B), wherein the plurality of elastic members (252A and 252B) are configured such that the plurality of forces (FA and FB) are different from each other (FA is zero while FB is 20N-50N), and the plurality of forces(FA, FB) flatten [0034] the semiconductor chip (202) (Chen et al., fig. 7A). The force applied to the portion 252B of the semiconductor chip (202) is considered as FB which is 20-50N [0032] while the force applied to the portion 252A of the semiconductor chip (202) is considered as FA which is 0N as the portion 252A does not contact the semiconductor chip (202).
Regarding claim 2, Chen teaches the method of claim 1, wherein applying the plurality of forces (FA, FB) to the plurality of points (252A’, 252B) of the semiconductor chip (202) through the plurality of elastic members (252A, 252B) comprises moving the plurality of elastic members (252A, 252B) into contact with the semiconductor chip (202) (fig. 7A, [0034]), and wherein front end portions (bottom portions of 252B, fig. 7A) of the plurality of elastic members (252B) form a plane (flat bottom, [0032]) when at least some of the plurality of elastic members (252A, 252B) prior to contact with the semiconductor chip (202) (Chen et al., fig., 7A).
Regarding claim 10, Chen teaches the method of claim 1, wherein the bonding of the semiconductor chip (202) to the object (230) further comprises transmitting heat (via a heating device, [0032]) to the plurality of points (252A’, 252B’) of the semiconductor chip (202) through the plurality of elastic members (252A, 252B) (Chen et al., [0032]).
Regarding claim 12, Chen teaches a method (fig. 3-10) of manufacturing a semiconductor package (300, fig. 10) [0038], the method comprising: moving [0032] a plurality of elastic members (252A and 252B, fig. 7A) [0032] toward a semiconductor chip (202, fig. 7A) [0032]; applying a plurality of forces (second downward force of 20N-50N, [0032]; hereinafter called FA and FB, see explanation below) to a plurality of points (areas corresponding with 252A and 252B, fig. 7A; hereinafter called 252A’ for the center of the chip and 252B’ for the edge of the chip) of the semiconductor chip (202) through the plurality of elastic members (252A, 252B); and bonding [0032] the semiconductor chip (202) to an object (230, fig. 7A) [0032] while the plurality of forces (FA, FB) are applied to the plurality of points (252A’, 252B’) of the semiconductor chip (202) through the plurality of elastic members (252A, 252B), wherein front end portions (bottom portions of 252B, fig. 7A) of the plurality of elastic members (252A, 252B) form a plane (flat bottom, [0032]) prior to contact with the semiconductor chip (202) (Chen et al., fig. 7A).
The force applied to the portion 252B of the semiconductor chip (202) is considered as FB which is 20-50N [0032] while the force applied to the portion 252A of the semiconductor chip (202) is considered as FA which is 0N as the portion 252A does not contact the semiconductor chip (202).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. US PGPub. 2024/0071982 as applied to claim 1 above, and further in view of Jeng et al. US PGPub. 2022/0102313. Regarding claim 9, Chen teaches the method of claim 1, wherein the bonding of the semiconductor chip (202) to the object (230) further comprises connecting (hybrid bond, [0038]) a front surface of the semiconductor chip (202) and the object (230) by applying the plurality of forces (FA, FB) to the plurality of points (252A’, 252B’) on a rear surface of the semiconductor chip (202) but fails to teach wherein the connecting is done by a plurality of solder balls between a front surface of the semiconductor chip (202) and the object (230). However, Jeng teaches a method of manufacturing a semiconductor package (fig. 7) comprising connecting a plurality of solder balls (44, fig. 7) [0022]; solder bonding, [0024]) between a front surface of the semiconductor chip (50A/B, fig. 7) [0024] and the object (46, fig. 7) [0024] (Jeng et al., fig. 7, [0024]). At the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in the art to make the simple substitution of the hybrid bonding used by Chen with the solder bonding used by Jeng because solder bonding and hybrid bonding are both well known in the art and such substitution is art recognized equivalence for the same purpose (for chip bonding, [0024]) to obtain predictable results such as excellent mechanical and electrical connection (see MPEP 2144.06).
Allowable Subject Matter
Claims 3-8, 11 and 13-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior arts of record taken alone or in combination neither anticipates nor renders obvious a method wherein “the plurality of elastic members are fixed to a plurality of through-holes of a housing, respectively, and applying the plurality of forces to the plurality of points of the semiconductor chip through the plurality of elastic members comprises applying a force to the housing” as recited in claims 3 and 13 in combination with the rest of the limitations of claims 1 and 12; a method wherein “the bonding of the semiconductor chip to the object further comprises applying a plurality of second forces to a plurality of points of the object through a plurality of second elastic members” as recited in claim 8 in combination with the rest of the limitations of claim 1; and
a method wherein “the bonding of the semiconductor chip to the object further comprises transmitting heat to the object by a vapor layer” as recited in claim 11 in combination with the rest of the limitations of claim 1.
Claims 4-7 and 14-16 are is also objected to as allowable for further limiting and depending upon allowable claims 3 and 13.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Baker et al. US PGPub. 2023/0317675 and Kumar et al. US PGPub. 2012/0217287 both teach a method of flattening a chip to prevent warping during a manufacturing a semiconductor package using heat.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NDUKA E OJEH whose telephone number is (571)270-0291. The examiner can normally be reached M-F; 9am - 5pm..
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/NDUKA E OJEH/Primary Examiner, Art Unit 2892
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