DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 9/19/2023 and 11/18/2025 were filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Specification
The abstract is consistent with the requirements set forth in the MPEP 608.01(b) The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1-4, 9-12 and 15-19 are rejected under 35 U.S.C. 103 as being unpatentable over Matsubara et al. US PGPub. 2016/0307854 in view of Yoshioka et al. US PGPub. 2019/0378810. Regarding claim 1, Matsubara teaches a semiconductor device (A1, fig. 7) [0032] comprising: a plurality of conductive members (31, 22, 22, 41, fig. 7) [0040]-[0041], [0044] and [0048] including a die pad (21 and 22, fig. 7) [0040]-[0041]; a first semiconductor element (111, fig. 7) [0035] and a second semiconductor element (112, fig. 7) [0035] each located on the die pad (21+22); an insulating element (12, fig. 7) [0035] electrically connected (via 71, fig. 7) [0034] to the first semiconductor element (111) and the second semiconductor element (112) and insulating the first semiconductor element (111) and the second semiconductor element (112) from each other; and a layer (72, fig. 7) [0040] interposed between the die pad (21+22) and the insulating element (12) and bonded (coated on [0040]) to the die pad (21+22), wherein the insulating element (12) is bonded (die bonding, [0040]) to the layer (72) (Matsubara et al., fig. 7). But Matsubara fails to teach wherein the layer (72) is an insulating substrate or teach an insulating substrate interposed between the die pad (21+22) and the insulating element and bonded to the die pad (21+22), wherein the insulating element (12) is bonded to the insulating substrate. However, Yoshioka teaches a semiconductor device (fig. 1) [0024] comprising an insulating substrate (3, fig. 1) [0033] interposed between the die pad (4, fig. 1) [0024] and a chip (1, fig. 1) [0024] and bonded to the die pad (4), wherein the chip (1) is bonded(via 2a, fig. 1) [0024] to the insulating substrate (3) (Yoshioka et al., fig. 1, [0033]). At the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in the art to substitute the layer of Matsubara for the insulating substrate as taught by Yoshioka because insulating substrates are well known in the art and such material/structure is art recognized and suitable for the intended purpose of improving both the heat dissipation and insultation property of the layer (Yoshioka et al., [0033]) (see MPEP 2144.07). As a result of the substitution, the layer 72 of Matsubara, now an insulating substrate (3 as taught by Yoshioka) is hereafter referred to as 72-3 (insulating substrate of Matsubara in view of Yoshioka).
Regarding claim 2, Matsubara in view of Yoshioka teaches the semiconductor device according to claim 1, wherein the die pad (21+22) includes a first die pad (21, fig. 7) [0040] and a second die pad (22, fig. 7) [0041] that are spaced apart from each other; the first semiconductor element (111) is bonded to the first die pad (21), and the second semiconductor element (112) is bonded to the second die pad (22) (Matsubara et al, fig. 7).
Regarding claim 3, Matsubara in view of Yoshioka teaches the semiconductor device according to claim 2, wherein the insulating substrate (72-3) is bonded to the first die pad (21) (Matsubara et al., fig. 7).
Regarding claim 4, Matsubara in view of Yoshioka teaches the semiconductor device according to claim 2, wherein the insulating substrate (72-3) is bonded to the second die pad (22) (Matsubara et al., fig. 7).
Regarding claim 9, Matsubara in view of Yoshioka teaches the semiconductor device according to claim 1, wherein the insulating substrate (72-3) is interposed between the die pad (21+22) and the first semiconductor element (111), and the first semiconductor element (111) is bonded (bonding layer, not shown, [0040]) to the insulating substrate (72-3) (Matsubara et al., fig. 7, [0040]).
Regarding claim 10, Matsubara in view of Yoshioka teaches the semiconductor device according to claim 1, wherein the insulating substrate (72-3) is interposed between the die pad (21+22) and the second semiconductor element (112), and the second semiconductor element (112) is bonded (bonding layer, not shown, [0040]) to the insulating substrate (Matsubara et al., fig. 7, [0040]).
Regarding claim 11, Matsubara in view of Yoshioka teaches the semiconductor device according to claim 1, wherein the insulating substrate (3) is located inward (fig. 1; edges of 3 are offset inwardly from edges of 4) from a periphery of the die pad (4) as viewed in a thickness direction of the insulating element (1) (Yoshioka et al., fig. 1). At the time before the effective filing of the claimed invention, it would have been obvious to one of ordinary skill in the art to substitute the layer of Matsubara for the insulating substrate as taught by Yoshioka because insulating substrates are well known in the art and such material/structure is art recognized and suitable for the intended purpose of improving both the heat dissipation and insultation property of the layer (Yoshioka et al., [0033]) (see MPEP 2144.07).
Regarding claim 12, Matsubara in view of Yoshioka teaches the semiconductor device according to claim 1, wherein the insulating element (12) is either of an inductive [0036] type or a capacitive type (Matsubara et al., fig. 7, [0036]).
Regarding claim 15, Matsubara in view of Yoshioka teaches the semiconductor device according to claim 1, wherein a voltage (600V, [0036]) applied to the second semiconductor (112) element is higher than a voltage (5V, [0036]) applied to the first semiconductor element (111) (Matsubara et al., fig. 7, [0036]).
Regarding claim 16, Matsubara in view of Yoshioka teaches the semiconductor device according to claim 1, further comprising a sealing resin (6, fig. 7) [0042] covering the first semiconductor element (111), the second semiconductor element (112), the insulating element (12) and at least a part of each of the plurality of conductive members (31, 21, 22, 41) (Matsubara et al., fig. 7)
Regarding claim 17, Matsubara in view of Yoshioka teaches the semiconductor device according to claim 16, wherein the first semiconductor element (111) and the second semiconductor element (112) are spaced apart from each other in a first direction (Y direction, fig. 2), the plurality of conductive members (31, 21, 22, 41) include a plurality of first terminals (31, fig. 2 and 7) [0044] exposed from one (left) side of the sealing resin (6) in the first (Y) direction and a plurality of second terminals (41, fig. 2 and 7) [0048] exposed from the other (right) side of the sealing resin (6) in the first (Y) direction, the first semiconductor element (111) electrically conducts (via 711, fig. 7) [0076] to the plurality of first terminals (31), and the second semiconductor element (112) electrically conducts (via 714, fig. 7) [0076] to the plurality of second terminals (41) (Matsubara et al., figs. 2 and 7)
Regarding claim 18, Matsubara in view of Yoshioka teaches the semiconductor device according to claim 17, wherein the plurality of first terminals (31) and the plurality of second terminals (41) are arranged along a second direction (X direction, fig. 2) orthogonal to the first (Y) direction (Matsubara et al., fig. 2)
Regarding claim 19, Matsubara in view of Yoshioka teaches the semiconductor device according to claim 18, wherein the die pad (21+22) includes a pad portion (21+22, fig. 7) and two suspension lead portions (51 and 52, fig. 7) [0053] connected to opposite (top and bottom, fig. 7) ends in the second (X) direction of the pad portion (21+22), the first semiconductor element (111) and the second semiconductor element (112) are located on the pad portion (21+22), and the two suspension lead portions (51+52) are exposed from at least one of opposite sides in the first (Y) direction of the sealing resin (6) (Matsubara et al., figs. 2 and 7).
Allowable Subject Matter
Claims 5-8 and 13-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior arts of record taken alone or in combination neither anticipates nor renders obvious a semiconductor device comprising “a first bonding layer interposed between the die pad and the insulating substrate; and a second bonding layer interposed between the insulating substrate and the insulating element, wherein a thickness of each of the first bonding layer and the second bonding layer is smaller than a thickness of the insulating substrate” as recited in claim 5 in combination with the rest of the limitations of claim 1; a semiconductor device wherein “the insulating element includes a first transmitter/receiver electrically conducting to the first semiconductor element, a second transmitter/receiver electrically conducting to the second semiconductor element, and a relay unit that transmits/receives a signal between the first transmitter/receiver and the second transmitter/receiver, and the relay unit is located closer to the insulating substrate than are the first transmitter/receiver and the second transmitter/receiver in the thickness direction of the insulating element” as recited in claim 13 in combination with the rest of the limitations of claims 1 and 12; and
a semiconductor device wherein “the insulating element includes a first insulating element and a second insulating element that are spaced apart from each other, the first insulating element includes: a first transmitter/receiver electrically conducting to the first semiconductor element; and a second transmitter/receiver that transmits/receives a signal to/from the first transmitter/receiver, the second insulating element includes: a third transmitter/receiver electrically conducting to the second transmitter/receiver; and a fourth transmitter/receiver that electrically conducts to the second semiconductor element and transmits/receives a signal to/from the third transmitter/receiver, and the second transmitter/receiver and the third transmitter/receiver are located closer to the insulating substrate than are the first transmitter/receiver and the fourth transmitter/receiver in the thickness direction of the insulating element” as recited in claim 14 in combination with the rest of the limitations of claims 1 and 12.
Claims 6-8 are also objected to as allowable for further limiting and depending upon allowable claim 5.
Conclusion
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/NDUKA E OJEH/Primary Examiner, Art Unit 2892