DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on 3/5/2026 has been entered and thus claims 1-21 are currently pending in this application.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 4, 6-8, 10, 12-18 and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Leitgeb et al. US PGPub. 2023/0298987. Regarding claim 1, Leitgeb teaches a substrate (100, fig. 1) [0082] comprising: a core layer (160, fig. 1) [0085]; at least one first dielectric layer (106, fig. 1; hereinafter called 106T, see examiner’s fig. 1) [0083] coupled to a first surface (1S, examiner’s fig. 1) of the core layer (160); at least one second dielectric layer (106, fig. 1; hereinafter called 106B, see examiner’s fig. 1) [0083] coupled to a second surface (2S, examiner’s fig. 1) of the core layer (160); a plurality of interconnects (126+172, fig. 1) [0093] located at least partially in the at least one first dielectric layer (106T); a region (108, fig. 1 and examiner’s fig. 1) [0084] comprising a plurality of block interconnects (at least 3 blocks of 170+120+122+124 arranged vertically, fig. 1; hereinafter called BI1-BI3, examiner’s fig. 1) [0093] and one or more block dielectric layers (106 withing the 108 region, fig. 1; hereinafter called 106-108, see examiner’s fig. 1), wherein the plurality of block interconnects (BI1, BI2, BI3) and the one or more block dielectric layers (106-108) define an interconnect block (108, fig. 1), wherein the one or more block dielectric layers (106-108) touch the at least one first dielectric layer (106T), wherein the plurality of block interconnects (BI1) are located at least partially in the one or more block dielectric layers (106-108), and wherein some of the block interconnects (BI3) from the plurality of block interconnects (BI1-BI3) touch the at least one first dielectric layer (106T); and a solder resist layer (162, fig. 1) [0088] coupled to the at least one first dielectric layer (106T) (Leitgeb et al., fig. 1).
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Examiner’s Fig. 1
Regarding claim 2, Leitgeb teaches the substrate of claim 1, wherein the solder resist layer (162) includes a first portion (162 over portion 110, fig. 1; hereinafter called 162-110) with a first thickness (hereinafter called T1, fig. 1) and a second portion (162 over portion 108, fig. 1; hereinafter called 162-108) with a second thickness (hereinafter called T2, fig. 1). 162 has the same thickness across all region 108 and 110, so T1 and T2 are the same thickness (Leitgeb et al., fig. 1).
Regarding claim 4, Leitgeb teaches the substrate of claim 1, wherein the interconnect block (108) includes a first block interconnect (BI1, examiner’s fig. 1) on a first metal layer (170, fig. 1), and a second block interconnect (BI2, examiner’s fig. 1) on a second metal layer (another 170, fig. 1), and wherein the first block interconnect (BI1) and/or the second block interconnect (BI2) is located laterally on a same horizontal plane as a via interconnect (172, fig. 1) from the plurality of interconnects (126+172) (Leitgeb et al., fig. 1). Regarding claim 6, Leitgeb teaches the substrate of claim 1, wherein the substrate (100) is implemented in a device selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device (antenna, [0061]), a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server [0081], an internet of things (IoT) device, and a device in an automotive vehicle (Leitgeb et al., [0081]). Regarding claim 7, Leitgeb teaches a package (fig. 1) comprising: a substrate (100, fig. 1) [0082] comprising: a core layer (160, fig. 1) [0085]; at least one first dielectric layer (106, fig. 1; hereinafter called 106T, see examiner’s fig. 1) [0083] coupled to a first surface (1S, examiner’s fig. 1) of the core layer (160); at least one second dielectric layer (106, fig. 1; hereinafter called 106B, see examiner’s fig. 1) [0083] coupled to a second surface (2S, examiner’s fig. 1) of the core layer (160); a plurality of interconnects (126+172, fig. 1) [0093] located at least partially in the at least one first dielectric layer (106T); a region (108, fig. 1 and examiner’s fig. 1) [0084] comprising a plurality of block interconnects (at least 3 blocks of 170+120+122+124 arranged vertically, fig. 1; hereinafter called BI1-BI3, examiner’s fig. 1) [0093] and one or more block dielectric layers (106 withing the 108 region, fig. 1; hereinafter called 106-108, see examiner’s fig. 1), wherein the plurality of block interconnects (BI1, BI2, BI3) and the one or more block dielectric layers (106-108) define an interconnect block (108, fig. 1), wherein the one or more block dielectric layers (106-108) touch the at least one first dielectric layer (106T), wherein the plurality of block interconnects (BI1) are located at least partially in the one or more block dielectric layers (106-108), and wherein some of the block interconnects (BI3) from the plurality of block interconnects (BI1-BI3) touch the at least one first dielectric layer (106T); and a solder resist layer (162, fig. 1) [0088] coupled to the at least one first dielectric layer (106T); a first integrated device (112, fig. 1) [0089] coupled to the substrate (100) through a first plurality of bump interconnects (164, fig. 1; hereinafter called 164-112) [0088]; and a second integrated device (114, fig. 1) [0089] coupled to the substrate (100) through a second plurality of bump interconnects (164, fig. 1; hereinafter called 164-112) [0088] (Leitgeb et al., fig. 1). Regarding claim 8, Leitgeb teaches the package of claim 7, wherein the solder resist layer (162) includes a first portion (162 over portion 110, fig. 1; hereinafter called 162-110) with a first thickness (hereinafter called T1, fig. 1) and a second portion (162 over portion 108, fig. 1; hereinafter called 162-108) with a second thickness (hereinafter called T2, fig. 1). 162 has the same thickness across all region 108 and 110, so T1 and T2 are the same thickness (Leitgeb et al., fig. 1). Regarding claim 10, Leitgeb teaches the package of claim 7, wherein the interconnect block (108) includes a first block interconnect (BI1, examiner’s fig. 1) on a first metal layer (170, fig. 1), and a second block interconnect (BI2, examiner’s fig. 1) on a second metal layer (another 170, fig. 1), and wherein the first block interconnect (BI1) and/or the second block interconnect (BI2) is located laterally on a same horizontal plane as a via interconnect (172, fig. 1) from the plurality of interconnects (126+172) (Leitgeb et al., fig. 1). Regarding claim 12, Leitgeb teaches the package of claim 7, wherein the first plurality of bump interconnects (164-112) includes a first plurality of pillar interconnects and/or a first plurality of solder interconnects [0089], and wherein the second plurality of bump interconnects (164-114) includes a second plurality of pillar interconnects and/or a second plurality of solder interconnects [0089] (Leitgeb et al., fig. 1, [0089]). Regarding claim 13, Leitgeb teaches the package of claim 7, wherein an electrical path [0089] between the first integrated device (112) and the second integrated device (114) includes the interconnect block (108)(Leitgeb et al., fig. 1, [0089]). Regarding claim 14, Leitgeb teaches the package of claim 13, wherein the electrical path [0089] between the first integrated device (112) and the second integrated device (114) includes (i) at least one interconnect (172 in region with 112) from the plurality of interconnects (172+126) of the substrate (100), (ii) at least one block interconnect (BI1) from the interconnect block (108) and (iii) at least one other interconnect (172 in region with 114) from the plurality of interconnects (172+126) of the substrate (100) (Leitgeb et al., fig. 1, [0089]). Regarding claim 15, Leitgeb teaches the package of claim 7, wherein the one or more block dielectric layers (106-108) of the interconnect block (108) and the at least one first dielectric layer (106) share a same dielectric layer (Leitgeb et al., fig. 1, [0083]). Regarding claim 16, Leitgeb teaches the package of claim 7, wherein the package is implemented in a device selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device (antenna, [0061]), a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server [0081], an internet of things (IoT) device, and a device in an automotive vehicle (Leitgeb et al., [0081]). Regarding claim 17, Leitgeb teaches a method for fabricating a substrate (100, fig. 1) [0082], comprising: providing a core layer (160, fig. 1) [0085]; forming at least one first dielectric layer (106, fig. 1; hereinafter called 106T, see examiner’s fig. 1) [0083] that is coupled to a first surface (1S, examiner’s fig. 1) of the core layer (160); forming at least one second dielectric layer (106, fig. 1; hereinafter called 106B, see examiner’s fig. 1) [0083] that is coupled to a second surface (1S, examiner’s fig. 1) of the core layer (160); forming a plurality of interconnects (126+172, fig. 1) [0093] located at least partially in the at least one first dielectric layer (106T); forming an interconnect block (108, fig. 1 and examiner’s fig. 1) [0084] comprising: one or more block dielectric layers (106 withing the 108 region, fig. 1; hereinafter called 106-108, see examiner’s fig. 1) that touch the at least one first dielectric layer (106T), and a plurality of block interconnects (at least 3 blocks of 170+120+122+124 arranged vertically, fig. 1; hereinafter called BI1-BI3, examiner’s fig. 1) [0093] over the at least one first dielectric layer (106T), wherein the plurality of block interconnects (BI1, BI2, BI3) are located at least partially in the one or more block dielectric layers (106-108), and wherein some of the block interconnects (BI3) from the plurality of block interconnects (BI1, BI2, BI3) touch the at least one first dielectric layer (106T); forming an additional first dielectric layer (106T, fig. 1) around and over the interconnect block (108); and forming a solder resist layer (162, fig. 1) [0088] that is coupled to the at least one first dielectric layer (106T) (Leitgeb et al., fig. 1). Regarding claim 18, Leitgeb teaches the method of claim 17, wherein the solder resist layer (162) includes a first portion (162 over portion 110, fig. 1; hereinafter called 162-110) with a first thickness (hereinafter called T1, fig. 1) and a second portion (162 over portion 108, fig. 1; hereinafter called 162-108) with a second thickness (hereinafter called T2, fig. 1). 162 has the same thickness across all region 108 and 110, so T1 and T2 are the same thickness (Leitgeb et al., fig. 1). Regarding claim 20, Leitgeb teaches the method of claim 17, wherein the interconnect block (108) includes a first block interconnect (BI1, examiner’s fig. 1) on a first metal layer (170, fig. 1), and a second block interconnect (BI2, examiner’s fig. 1) on a second metal layer (another 170, fig. 1), and wherein the first block interconnect (BI1) and/or the second block interconnect (BI2) is located laterally on a same horizontal plane as a via interconnect (172, fig. 1) from the plurality of interconnects (126+172) (Leitgeb et al., fig. 1).
Allowable Subject Matter
Claims 3, 5, 9, 11, 19 and 21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior arts of record taken alone or in combination neither anticipates nor renders obvious a substrate, a package and a method wherein “the second portion of the solder resist layer is located vertically over at least part of the interconnect block, and wherein the second thickness of the second portion is less than the first thickness of the first portion” as recited in claims 3, 9 and 19 in combination with the rest of the limitations of claims 1-2, 7-8 and 17-18, respectively; and
a substrate, a package and a method wherein “a first surface of the at least one first dielectric layer located over the interconnect block is located away from a surface of the core layer by a first distance, wherein a second surface of the at least one first dielectric layer that is not located over the interconnect block is located away from the surface of the core layer by a second distance, and wherein the first distance is greater than the second distance” as recited in claims 5, 11 and 21 in combination with the rest of the limitations of claims 1, 7 and 17, respectfully.
Response to Arguments
Applicant’s arguments with respect to claims 1-21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NDUKA E OJEH whose telephone number is (571)270-0291. The examiner can normally be reached M-F; 9am - 5pm..
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/NDUKA E OJEH/Primary Examiner, Art Unit 2892