DETAILED ACTION
This office action is in response to the election filed 5/13/2026.
Currently, claims 1-28 are pending. Of these, claims 16-28 have been withdrawn from consideration.
Election/Restrictions
Applicant’s election without traverse of Group I, Species I is acknowledged.
Claim Objections
Claim 3 is objected to because of the following informalities: In lines 3 and 8, the term “from” is used, which does not make sense in the context of the claim. Likely, the term is meant to be “form”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 5 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 recites the limitation “wherein the vertical connector comprises a trench via extending in the X direction” is unclear in light of the disclosure. Namely, the disclosure presents the vertical connector and the trench via as two separate elements. See e.g. FIG. 5, where the trench via is reference numeral 510 and the vertical connector is reference numeral 512. See also para. [0042], which lists them as separate elements: “The integrated circuit 500 also includes a deep trench via 510 and a vertical connector 512”. Thus, it is not clear how the trench via could be considered to be a part of the vertical connector as a whole, as claimed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-8, 11-13 and 15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Sinha et al. (US 2024/0105709, cited in IDS).
Pertaining to claim 1, Sinha shows, with reference to FIG. 1-6, a semiconductor structure, comprising:
a first field effect transistor (FET) (comprising active region 106) of a first charge carrier type (para. [0074]), comprising a first source/drain (S/D) region (124E), a second S/D region (124F), and a first gate (116B);
a second FET (comprising active region 104) of a second charge carrier type (para. [0074]), disposed above the first FET in a Z direction and comprising a third S/D region (124B), a fourth S/D region (124C), and a second gate (108B);
a frontside (FS) metal (FM) layer (112) disposed above the second FET in the Z direction and comprising a plurality of FM conductors (112A-D) extending in an X direction;
a backside (BS) metal (BM) layer (120) disposed below the first FET in the Z direction and comprising a plurality of BM conductors (120A-C) extending in the X direction; and
a vertical connector (600) extending in the Z direction, wherein the vertical connector electrically couples one of the plurality of BM conductors (120A) to the third S/D region, the fourth S/D region, or the second gate (FIG. 6).
Pertaining to claim 2, Sinha shows the first gate comprises a first gate-all-around (GAA) structure comprising a first GAA region and wherein the second gate comprises a second GAA structure comprising a second GAA region (FIG. 5).
Pertaining to claim 3, Sinha shows the first FET comprises a first plurality of nanosheet channels (para. [0074]) extending in the X direction and spaced apart from each other in the Z direction to form a first vertical stack (FIG. 5 and 6), each channel electrically coupling the first S/D region to the second S/D region through the first GAA region and being separated from the first GAA region by a first dielectric material (these are features of a MOS transistor, which is the disclosed transistor type (para. [0074])); and the second FET comprises a second plurality of nanosheet channels (para. [0074]) extending in the X direction and spaced apart from each other in the Z direction to form a second vertical stack disposed above the first vertical stack in the Z direction (FIG. 5 and 6), each channel electrically coupling the third S/D region to the fourth S/D region through the second GAA region and being separated from the second GAA region by a second dielectric material (these are features of a MOS transistor, which is the disclosed transistor type (para. [0074])).
Pertaining to claim 4, Sinha shows the vertical connector provides a first voltage from the one of the plurality of BM conductors to the third S/D region, the fourth S/D region, or the second gate (para. [0078], [0081]).
Pertaining to claim 5, the vertical connector may be considered to be a trench via as it is a via formed in a trench. It is a three-dimensional object and thus extends at least to an extent in the X direction.
Pertaining to claim 6, Sinha shows the vertical connector extends in the Z direction at least from a bottom surface of the first gate to a top surface of the second gate (FIG. 6).
Pertaining to claim 7, Sinha shows a second vertical connector (110) that electrically couples the second S/D region to the fourth S/D region by direct contact with both the second S/D region and the fourth S/D region (FIG. 4).
Pertaining to claim 8, Sinha shows the second vertical connector is electrically coupled to one of the plurality of FM conductors, another of the plurality of BM conductors, or both (FIG. 3).
Pertaining to claim 11, Sinha shows the semiconductor structure comprises a standard cell (para. [0005]).
Pertaining to claim 12, Sinha shows the plurality of FM conductors extending in the X direction consists of four or fewer FM conductors extending in the X direction (para. [0079]).
Pertaining to claim 13, Sinha shows the plurality of BM conductors extending in the X direction consists of four or fewer BM conductors extending in the X direction (para. [0079]).
Pertaining to claim 15, Sinha shows the plurality of BM conductors extending in the X direction consists of three or fewer BM conductors extending in the X direction (para. [0079]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Sinha.
Although Sinha does not explicitly teach the three or fewer FM conductors, Sinha does teach that any number of such conductors may be used as allowed according to design and manufacturing constraints.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the invention of Sinha by using three FM conductors, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Allowable Subject Matter
Claims 9 and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art does not teach the structure as defined in claim 1, and further comprising a backside jumper that is disposed below the first gate and isolated from the first gate by a dielectric material, that electrically couples the first S/D region to the second S/D region. Although Do (US 2021/0242125, cited in IDS) discloses a backside jumper used in a similar application, it does not meet all of the limitations of the backside jumper defined in claim 9, particularly the coupling of the first and second S/D regions. Thus, claim 9, as well as claim 10 dependent thereon, is found to contain allowable subject matter.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Doornbos et al. (US 2024/0105725) and Chakraborty et al. (US 2025/0008740) disclose inventions similar to Applicant’s.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL M LUKE whose telephone number is (571)270-1569. The examiner can normally be reached Monday-Friday, 9am-5pm, EST.
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/DANIEL LUKE/Primary Examiner, Art Unit 2896
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