DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement(s) submitted on September 19, 2023 and February 7, 2025 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Claim Objections
Claims 4 and 19 are objected to because of the following informalities:
“to from a first vertical stack” should read “to form a first vertical stack” (claim 4, line 3 and claim 19, lines 3-4);
“to from a second vertical stack” should read “to form a second vertical stack” (claim 4, lines 8-9 and claim 19, lines 8-9);
“second” should be inserted between “a” and “plurality” (claim 19, line 7).
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 5-10, 13-17, 20-24 and 27 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2023/0067311 A1 (hereinafter “Lai”).
Regarding claim 1, Lai discloses in Fig. 1A and related text a semiconductor structure, comprising:
at least one complementary field effect transistor (CFET) structure (100; [0001] and [0026]), comprising:
a first field effect transistor (FET) (“an NMOS transistor”; [0026]) of a first charge carrier type (n-type), comprising a first source/drain (S/D) region (80n (portion thereof enclosed by source electrode 132n); [0027]), a second S/D region (80n (portion thereof enclosed by drain electrode 134n); [0027]), and a first gate (the lower one of the two gate conductors that together form gate conductor 150; [0026]);
a second FET (“a PMOS transistor”; [0026]) of a second charge carrier type (p-type), disposed above the first FET in a Z direction and comprising a third S/D region (80p (portion thereof enclosed by source electrode 132p); [0027]), a fourth S/D region (80p (portion thereof enclosed by drain electrode 134p); [0027]), and a second gate (the upper one of the two gate conductors that together form gate conductor 150; [0026]);
a frontside (FS) metal (FM) layer (“a metal layer M0”; [0025]) disposed above the second FET in the Z direction and comprising an FM conductor (20F; [0028]) extending in an X direction;
a backside (BS) metal (BM) layer (“a metal layer BM0”; [0025]) disposed below the first FET in the Z direction and comprising a BM conductor (142B; [0030]) extending in the X direction; and
a vertical connector (VTB; [0030]) extending in the Z direction, wherein the vertical connector electrically couples the BM conductor to the FM conductor.
Regarding claim 2, Lai discloses the FM conductor is electrically coupled to at least one of the third S/D region, the fourth S/D region, or the second gate (Fig. 1A; [0027] and [0030]).
Regarding claim 5, Lai discloses the vertical connector provides a first supply voltage from the BM conductor to the FM conductor ([0030]).
Regarding claim 6, Lai discloses the semiconductor structure comprises a standard cell (an inverter circuit; [0026]), wherein the FM conductor is one of a plurality of FM conductors (20F, 120F, 140F; Fig. 1A; [0028]-[0029]) extending in the X direction and spaced apart from each other along a Y direction, and wherein the BM conductor is one of a plurality of BM conductors (20B, 120B, 142B; Fig. 1A; [0028]-[0030]) extending in the X direction and spaced apart from each other along the Y direction.
Regarding claim 7, Lai discloses the plurality of FM conductors extending in the X direction consists of four or fewer FM conductors extending in the X direction.
Regarding claim 8, Lai discloses the plurality of BM conductors extending in the X direction consists of four or fewer BM conductors extending in the X direction.
Regarding claim 9, Lai discloses the plurality of FM conductors extending in the X direction consists of three or fewer FM conductors extending in the X direction.
Regarding claim 10, Lai discloses the plurality of BM conductors extending in the X direction consists of three or fewer BM conductors extending in the X direction.
Regarding claim 13, Lai discloses in Fig. 1A and related text a semiconductor structure, comprising:
a frontside (FS) metal (FM) layer (“a metal layer M0”; [0025]) comprising a plurality of FM conductors (20F, 120F, 140F; [0028]-[0029]) extending in an X direction and separated from each other along a Y direction;
a backside (BS) metal (BM) layer (“a metal layer BM0”; [0025]) disposed below the FM layer in a Z direction and comprising a plurality of BM conductors (20B, 120B, 142B; [0028]-[0030]) extending in the X direction and separated from each other along the Y direction; and
a vertical connector (VTB; [0030]) extending in the Z direction, wherein the vertical connector electrically couples a first BM conductor (142B) of the plurality of BM conductors to a first FM conductor (20F) of the plurality of FM conductors.
Regarding claim 14, Lai discloses the first BM conductor provides a first supply voltage (VDD) to the semiconductor structure and wherein the vertical connector provides the first supply voltage from the first BM conductor to the first FM conductor ([0027] and [0030]).
Regarding claim 15, Lai discloses a second BM conductor (20B) of the plurality of BM conductors provides a second supply voltage (VSS) to the semiconductor structure ([0027]).
Regarding claim 16, Lai discloses in Fig. 1A and related text a method of fabricating a semiconductor structure, the method comprising:
providing at least one complementary field effect transistor (CFET) structure (100; [0001] and [0026]), comprising:
providing a first field effect transistor (FET) (“an NMOS transistor”; [0026]) of a first charge carrier type (n-type), comprising a first S/D region (80n (portion thereof enclosed by source electrode 132n); [0027]), a second S/D region (80n (portion thereof enclosed by drain electrode 134n); [0027]), and a first gate (the lower one of the two gate conductors that together form gate conductor 150; [0026]);
providing a second FET (“a PMOS transistor”; [0026]) of a second charge carrier type (p-type), disposed above the first FET in a Z direction and comprising a third S/D region (80p (portion thereof enclosed by source electrode 132p); [0027]), a fourth S/D region (80p (portion thereof enclosed by drain electrode 134p); [0027]), and a second gate (the upper one of the two gate conductors that together form gate conductor 150; [0026]);
providing a frontside (FS) metal (FM) layer (“a metal layer M0”; [0025]) disposed above the second FET in the Z direction and comprising an FM conductor (20F; [0028]) extending in an X direction;
providing a vertical connector (VTB; [0030]) extending in the Z direction and being electrically coupled to the FM conductor; and
providing a backside (BS) metal (BM) layer (“a metal layer BM0”; [0025]) disposed below the first FET in the Z direction and comprising a BM conductor (142B; [0030]) extending in the X direction and being electrically coupled to the vertical connector.
Regarding claim 17, Lai discloses providing an electrical connection from the FM conductor to at least one of the third S/D region, the fourth S/D region, or the second gate (Fig. 1A; [0027] and [0030]).
Regarding claim 20, Lai discloses providing additional FM conductors to create a plurality of FM conductors (20F, 120F, 140F; Fig. 1A; [0028]-[0029]) extending in the X direction and spaced apart from each other along a Y direction; and providing additional BM conductors to create a plurality of BM conductors (20B, 120B, 142B; Fig. 1A; [0028]-[0030]) extending in the X direction and spaced apart from each other along the Y direction.
Regarding claim 21, Lai discloses the plurality of FM conductors extending in the X direction consists of four or fewer FM conductors extending in the X direction.
Regarding claim 22, Lai discloses the plurality of BM conductors extending in the X direction consists of four or fewer BM conductors extending in the X direction.
Regarding claim 23, Lai discloses the plurality of FM conductors extending in the X direction consists of three or fewer FM conductors extending in the X direction.
Regarding claim 24, Lai discloses the plurality of BM conductors extending in the X direction consists of three or fewer BM conductors extending in the X direction.
Regarding claim 27, Lai discloses in Fig. 1A and related text a method of fabricating a semiconductor structure, the method comprising:
providing a frontside (FS) metal (FM) layer (“a metal layer M0”; [0025]) comprising a plurality of FM conductors (20F, 120F, 140F; [0028]-[0029]) extending in an X direction and separated from each other along a Y direction;
providing a vertical connector (VTB; [0030]) extending in a Z direction and being electrically coupled to one (20F) of the plurality of FM conductors; and
providing a backside (BS) metal (BM) layer (“a metal layer BM0”; [0025]) disposed below the FM layer in the Z direction and comprising a plurality of BM conductors (20B, 120B, 142B; [0028]-[0030]) extending in the X direction and separated from each other along the Y direction, one (142B) of the plurality of BM conductors being electrically coupled to the vertical connector ([0030]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3, 4, 18 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lai in view of US 2022/0059414 A1 (hereinafter “Yang”).
Regarding claim 3, Lai discloses the semiconductor structure of claim 1.
Lai does not explicitly disclose, in the embodiment of Fig. 1A, the first gate comprises a first gate-all-around (GAA) structure comprising a first GAA region and wherein the second gate comprises a second GAA structure comprising a second GAA region.
Yang teaches in Figs. 1A-1B and related text the first gate (112A; [0024], [0029] and [0042]) comprises a first gate-all-around (GAA) structure comprising a first GAA region and wherein the second gate (112B; [0029] and [0042]) comprises a second GAA structure comprising a second GAA region.
Lai and Yang are analogous art because they both are directed to complementary field effect transistors and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lai with the specified features of Yang because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the first gate to comprise a first gate-all-around (GAA) structure comprising a first GAA region and to form the second gate to comprise a second GAA structure comprising a second GAA region, as taught by Yang, in order to improve gate control by increasing gate-channel coupling, reduce off-state current, and reduce short-channel effects (Yang: [0024]).
Regarding claim 4, Lai in view of Yang disclose the semiconductor structure of claim 3.
Lai does not explicitly disclose, in the embodiment of Fig. 1A, the first FET comprises a first plurality of nanosheet channels extending in the X direction and spaced apart from each other in the Z direction to form a first vertical stack, each channel electrically coupling the first S/D region to the second S/D region through the first GAA region and being separated from the first GAA region by a first dielectric material; and the second FET comprises a second plurality of nanosheet channels extending in the X direction and spaced apart from each other in the Z direction to form a second vertical stack disposed above the first vertical stack in the Z direction, each channel electrically coupling the third S/D region to the fourth S/D region through the second GAA region and being separated from the second GAA region by a second dielectric material.
Yang teaches in Figs. 1A-1B and related text the first FET (102A; [0028]) comprises a first plurality of nanosheet channels (122A; [0032]) extending in the X direction and spaced apart from each other in the Z direction to form a first vertical stack, each channel electrically coupling the first S/D region (110A (e.g., at the left end of the nanosheets 122A in Fig. 1B); [0037]) to the second S/D region (110A (e.g., at the right end of the nanosheets 122A in Fig. 1B); [0037]) through the first GAA region (112A; [0042]) and being separated from the first GAA region by a first dielectric material (114A; [0044]); and
the second FET (102B; [0028]) comprises a second plurality of nanosheet channels (122B; [0032]) extending in the X direction and spaced apart from each other in the Z direction to form a second vertical stack disposed above the first vertical stack in the Z direction, each channel electrically coupling the third S/D region (110B (e.g., at the left end of the nanosheets 122B in Fig. 1B); [0037]) to the fourth S/D region (110B (e.g., at the right end of the nanosheets 122B in Fig. 1B); [0037]) through the second GAA region (112B; [0042]) and being separated from the second GAA region by a second dielectric material (114B; [0044]).
Lai and Yang are analogous art because they both are directed to complementary field effect transistors and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lai in view of Yang with the specified features of Yang because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the first FET to comprise a first plurality of nanosheet channels extending in the X direction and spaced apart from each other in the Z direction to form a first vertical stack, each channel electrically coupling the first S/D region to the second S/D region through the first GAA region and being separated from the first GAA region by a first dielectric material; and to form the second FET to comprise a second plurality of nanosheet channels extending in the X direction and spaced apart from each other in the Z direction to form a second vertical stack disposed above the first vertical stack in the Z direction, each channel electrically coupling the third S/D region to the fourth S/D region through the second GAA region and being separated from the second GAA region by a second dielectric material, as taught by Yang, in order to improve gate control by increasing gate-channel coupling, reduce off-state current, and reduce short-channel effects (Yang: [0024]).
Regarding claim 18, Lai discloses the method of claim 16.
Lai does not explicitly disclose, in the embodiment of Fig. 1A, providing the first FET comprises providing a gate-all-around (GAA) FET comprising a first GAA region and providing the second FET comprises providing a GAA FET comprising a second GAA region.
Yang teaches in Figs. 1A-1B and related text providing the first FET (102A; [0028]) comprises providing a gate-all-around (GAA) FET comprising a first GAA region (112A; [0042]) and providing the second FET (102B; [0028]) comprises providing a GAA FET comprising a second GAA region (112B; [0042]).
Lai and Yang are analogous art because they both are directed to complementary field effect transistors and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lai with the specified features of Yang because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to provide the first FET by providing a gate-all-around (GAA) FET comprising a first GAA region and to provide the second FET by providing a GAA FET comprising a second GAA region, as taught by Yang, in order to improve gate control by increasing gate-channel coupling, reduce off-state current, and reduce short-channel effects (Yang: [0024]).
Regarding claim 19, Lai in view of Yang disclose the method of claim 18.
Lai does not explicitly disclose, in the embodiment of Fig. 1A, providing the first FET comprises providing a first plurality of nanosheet channels extending in the X direction and spaced apart from each other in the Z direction to form a first vertical stack, each channel electrically coupling the first S/D region to the second S/D region through the first GAA region and being separated from the first GAA region by a first dielectric material; and providing the second FET comprises providing a second plurality of nanosheet channels extending in the X direction and spaced apart from each other in the Z direction to form a second vertical stack disposed above the first vertical stack in the Z direction, each channel electrically coupling the third S/D region to the fourth S/D region through the second GAA region and being separated from the second GAA region by a second dielectric material.
Yang teaches in Figs. 1A-1B and related text providing the first FET (102A; [0028]) comprises providing a first plurality of nanosheet channels (122A; [0032]) extending in the X direction and spaced apart from each other in the Z direction to form a first vertical stack, each channel electrically coupling the first S/D region (110A (e.g., at the left end of the nanosheets 122A in Fig. 1B); [0037]) to the second S/D region (110A (e.g., at the right end of the nanosheets 122A in Fig. 1B); [0037]) through the first GAA region (112A; [0042]) and being separated from the first GAA region by a first dielectric material (114A; [0044]); and
providing the second FET (102B; [0028]) comprises providing a second plurality of nanosheet channels (122B; [0032]) extending in the X direction and spaced apart from each other in the Z direction to form a second vertical stack disposed above the first vertical stack in the Z direction, each channel electrically coupling the third S/D region (110B (e.g., at the left end of the nanosheets 122B in Fig. 1B); [0037]) to the fourth S/D region (110B (e.g., at the right end of the nanosheets 122B in Fig. 1B); [0037]) through the second GAA region (112B; [0042]) and being separated from the second GAA region by a second dielectric material (114B; [0044]).
Lai and Yang are analogous art because they both are directed to complementary field effect transistors and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lai in view of Yang with the specified features of Yang because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to provide the first FET by providing a first plurality of nanosheet channels extending in the X direction and spaced apart from each other in the Z direction to form a first vertical stack, each channel electrically coupling the first S/D region to the second S/D region through the first GAA region and being separated from the first GAA region by a first dielectric material; and to provide the second FET by providing a second plurality of nanosheet channels extending in the X direction and spaced apart from each other in the Z direction to form a second vertical stack disposed above the first vertical stack in the Z direction, each channel electrically coupling the third S/D region to the fourth S/D region through the second GAA region and being separated from the second GAA region by a second dielectric material, as taught by Yang, in order to improve gate control by increasing gate-channel coupling, reduce off-state current, and reduce short-channel effects (Yang: [0024]).
Allowable Subject Matter
Claims 11, 12, 25 and 26 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art of record, individually or in combination, does not teach or suggest “a second vertical connector that electrically couples the second S/D region to the fourth S/D region by direct contact with both the second S/D region and the fourth S/D region” as recited in claim 11, and “providing a second vertical connector that electrically couples the second S/D region to the fourth S/D region by direct contact with both the second S/D region and the fourth S/D region” as recited in claim 25. Claim 12 depends from claim 11 and therefore would be allowable at least by virtue of its dependency. Claim 26 depends from claim 25 and therefore would be allowable at least by virtue of its dependency.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER M ALBRECHT whose telephone number is (571)272-7813. The examiner can normally be reached M-F 9:30 AM - 6:30 PM (CT).
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/PETER M ALBRECHT/Primary Examiner, Art Unit 2811