DETAILED ACTION
This action is responsive to the application No. 18/470,250 filed on September 19, 2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election with traverse of the Group I invention and Species 4 reading on Fig. 4 in the reply filed on 01/08/2026 is acknowledged. The Applicants indicated that claims 1-14 read on the elected species. However, claims 3, 4, 10, and 11 read on a non-elected species of the claimed invention. For instance, claims 3 and 10 recite “the plurality of via interconnects include a second via interconnect coupled to the first via interconnect without a pad between the first via interconnect and the second via interconnect”. This feature however, is exclusive of the originally defined species 2, 3, 5, and 6. Claims 3, 4, 10, 11, and 15-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention/species, there being no allowable generic or linking claim. Accordingly, pending in this Office action are claims 1-20.
The traversal is on the grounds that a more appropriate species requirement may be the following species grouping:
Species 1: Fig. 1 and Fig. 4
Species 2: Fig. 2 and Fig. 5
Species 3: Fin. 3 and Fig. 6
The examiner agrees with the applicant. Species 1 proposed by the applicant, including Figs. 1 and 4 is being examined.
The restriction requirement is still deemed proper and is, therefore, made FINAL.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5-8, and 12-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kang (US 2020/0013706).
Regarding Claim 1, Kang (see, e.g., Fig. 2), teaches a substrate 202 (see, e.g., par. 0029) comprising:
at least one dielectric layer 205 (see, e.g., par. 0031); and
a plurality of interconnects 250/252/254 located at least partially in the at least one dielectric layer 205 (see, e.g., pars. 0032, 0035, 0039),
wherein:
the plurality of interconnects 250/252/254 include a plurality of via interconnects 250 (see, e.g., par. 0039), and
the plurality of via interconnects 250 include a first via interconnect 250 comprising a first via wall that is approximately vertical.
Regarding Claim 5, Kang teaches all aspects of claim 1. Kang (see, e.g., Fig. 2), teaches that:
the plurality of via interconnects 250 include a second via interconnect 250 that is located laterally to the first via interconnect 250, and
the first via interconnect 250 has a first diameter and the second via interconnect 250 has a second diameter.
Regarding Claim 6, Kang teaches all aspects of claim 1. Kang (see, e.g., Fig. 2), teaches:
a core layer 203 (see, e.g., par. 0032); and
a plurality of core via interconnects 230 located in the core layer 203 (see, e.g., par. 0032).
Regarding Claim 7, Kang teaches all aspects of claim 6. Kang (see, e.g., Fig. 2), teaches that the plurality of core via interconnects 230 include a first core via interconnect 230 comprising a core via wall that is tapered (see, e.g., par. 0032).
Regarding Claim 8, Kang (see, e.g., Fig. 2), teaches a package 200 (see, e.g., par. 0029) comprising:
an integrated device 208 (see, e.g., par. 0029); and
a substrate 202 coupled to the integrated device 208, the substrate 202 (see, e.g., par. 0029) comprising:
at least one dielectric layer 205 (see, e.g., par. 0031); and
a plurality of interconnects 250/252/254 located at least partially in the at least one dielectric layer 205 (see, e.g., pars. 0032, 0035, 0039),
wherein:
the plurality of interconnects 250/252/254 include a plurality of via interconnects 250 (see, e.g., par. 0039), and
the plurality of via interconnects 250 include a first via interconnect 250 comprising a first via wall that is approximately vertical.
Regarding Claim 12, Kang teaches all aspects of claim 8. Kang (see, e.g., Fig. 2), teaches that:
the plurality of via interconnects 250 include a second via interconnect 250 that is located laterally to the first via interconnect 250, and
the first via interconnect 250 has a first diameter and the second via interconnect 250 has a second diameter.
Regarding Claim 13, Kang teaches all aspects of claim 8. Kang (see, e.g., Fig. 2), teaches:
a core layer 203 (see, e.g., par. 0032); and
a plurality of core via interconnects 230 located in the core layer 203 (see, e.g., par. 0032).
Regarding Claim 14, Kang teaches all aspects of claim 13. Kang (see, e.g., Fig. 2), teaches that the plurality of core via interconnects 230 include a first core via interconnect 230 comprising a core via wall that is tapered (see, e.g., par. 0032).
Claims 1, 2, 8, and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jang (US 2023/0039094).
Regarding Claim 1, Jang (see, e.g., Figs. 1-2), teaches a substrate 100 (see, e.g., par. 0022) comprising:
at least one dielectric layer 110a (see, e.g., par. 0025); and
a plurality of interconnects 300 located at least partially in the at least one dielectric layer 110a (see, e.g., pars. 0022, 0025),
wherein:
the plurality of interconnects 300 include a plurality of via interconnects 30 (see, e.g., par. 0039), and
the plurality of via interconnects 30 include a first via interconnect 30 comprising a first via wall that is approximately vertical.
Regarding Claim 2, Jang teaches all aspects of claim 1. Jang (see, e.g., Figs.1- 2), teaches that the first via interconnect 30 extends through a metal layer (i.e., layer of wiring 120a) of the substrate 110 without touching a pad.
Regarding Claim 8, Jang (see, e.g., Figs. 1-2), teaches a package 10 (see, e.g., par. 0022) comprising:
an integrated device 200 (see, e.g., par. 0022); and
a substrate 100 coupled to the integrated device 200, the substrate 100 (see, e.g., par. 0022) comprising:
at least one dielectric layer 110a (see, e.g., par. 0025); and
a plurality of interconnects 300 located at least partially in the at least one dielectric layer 110a (see, e.g., pars. 0022, 0025),
wherein:
the plurality of interconnects 300 include a plurality of via interconnects 300 (see, e.g., par. 0039), and
the plurality of via interconnects 30 include a first via interconnect 30 comprising a first via wall that is approximately vertical.
Regarding Claim 9, Jang teaches all aspects of claim 8. Jang (see, e.g., Figs.1- 2), teaches that the first via interconnect 30 extends through a metal layer (i.e., layer of wiring 120a) of the substrate 110 without touching a pad.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nelson Garcés whose telephone number is (571)272-8249. The examiner can normally be reached on M-F 9:00 AM - 5:30 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on (571)272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Nelson Garces/
Primary Examiner, Art Unit 2814