DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the Application filed on 09/19/2023.
Currently, claims 1-20 are examined as below.
Information Disclosure Statement
Acknowledgment is made of applicant's Information Disclosure Statements (IDS) filed on 09/19/2023 and 09/20/2023. The IDS have been considered.
Claim Objections
Claim 12 is objected to because of the following informalities:
Regarding claim 12, in line 1, “part of the dielectric layer” should read “a part of the dielectric layer.”
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4-6, 8-11, 13-16 and 18-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2022/0310398 A1 to Lin et al. (“Lin”).
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Regarding independent claim 1, Lin in Figs. 16B, 17B, 28C and Annotated Fig. 28C teaches a semiconductor device (Fig. 28C) comprising:
at least one epitaxial source/drain region 148 (Fig. 28C, ¶ 50, ¶ 56, abstract & claim 1, source/drain region 148 is an epitaxy source/drain region); and
a dielectric layer 180 (Fig. 28C, ¶ 53 & ¶ 42, dielectric layer 180) disposed in a trench 78 (Figs. 16B, 17B, Annotated Fig. 28C & ¶ 39, trench 78 is the space within the region 148 that accommodates the dielectric layer 180) in the at least one epitaxial source/drain region 148.
Regarding claim 2, Lin in Fig. 28C further teaches the dielectric layer 180 comprises one of a material with a negative coefficient of thermal expansion and a material with a positive coefficient of thermal expansion (¶ 53 & ¶ 42, the dielectric layer 180 includes silicon nitride, which is the same positive CTE dielectric material as the Applicant purported in paragraph 63 in the specification of the present application).
Regarding claim 4, Lin in Fig. 28C teaches the at least one epitaxial source/drain region 148 corresponds to an n-type transistor (¶ 29) and the dielectric layer 180 comprises a material with a positive coefficient of thermal expansion (¶ 53 & ¶ 42, the dielectric layer 180 includes silicon nitride, which is the same positive CTE dielectric material as the Applicant purported in paragraph 63 in the specification of the present application).
Regarding claim 5, Lin in Figs. 28C further teaches the dielectric layer 180 is disposed on a first side (Fig. 28C, inner left side) of the at least one epitaxial source/drain region 148.
Regarding claim 6, Lin in Fig. 28C further teaches a source/drain contact 194 (Fig. 28C & ¶ 51, source/drain contact plugs 194) disposed on a second side (Fig. 28C, inner right side) of the at least one epitaxial source/drain region 148, wherein the second side is opposite the first side (Fig. 28C, the inner left side and the inner right side of the region 148 are opposite to each other).
Regarding claim 8, Lin in Annotated 28C further teaches a first portion (Annotated Fig. 28C, lower portion) of the trench 78 is disposed in the at least one epitaxial source/drain region 148 and a second portion (Annotated Fig. 28C, upper portion) of the trench 78 is disposed in an additional dielectric layer 176 (Annotated Fig. 28C, ¶ 54 & ¶ 9, inter-layer dielectric (ILD) 176) on the at least one epitaxial source/drain region 148.
Regarding claim 9, Lin in Annotated Fig. 28C further teaches a first portion (Annotated Fig. 28C , lower portion) of the dielectric layer 180 is disposed in the first portion (i.e., lower portion) of the trench 78 and a second portion (Annotated Fig. 28C, upper portion) of the dielectric layer 180 is disposed in the second portion (i.e., upper portion) of the trench 78.
Regarding claim 10, Lin in Annotated Fig. 28C further teaches a spacer layer 190 (Annotated Fig. 28C & ¶ 52, capping layer 190 formed of titanium nitride that separates the layers 180 and 192) disposed adjacent the second portion (i.e., upper portion) of the dielectric layer 180.
Regarding claim 11, Lin in Fig. 24B and Annotated Fig. 28C further teaches a stacked structure STK (Annotated Fig. 28C & ¶ 50, stacked structure STK of FinFET 196 (corresponding to GAA transistor 96 in Fig. 24B) includes layers 22B, 44, 62, 68) comprising a plurality of gate structures 36 (Fig. 24B, Annotated Fig. 28C & ¶ 36, gate electrodes 68) alternately stacked with a plurality of channel layers 22B (Fig. 24B & Annotated Fig. 28C, nanostructures 22B are channels), wherein the at least one epitaxial source/drain region 148 is disposed on a side of the stacked structure STK.
Regarding independent claim 13, Lin in Figs. 16B, 17B, 24B, 28C and Annotated Fig. 28C teaches a semiconductor device (Fig. 28C) comprising:
a first nanosheet structure STK (Annotated Fig. 28C, ¶ 29, ¶ 33, ¶ 50, ¶ 56, ¶ 1 & claim 6 disclose the left stack STK of FinFet 196 is a nano sheet structure) comprising a first plurality of gate structures 68 (Annotated Fig. 28C, ¶ 36 & ¶ 50, gate electrodes 68 of FinFET 196 (corresponding to GAA transistor 96 in Fig. 24B)) alternately stacked with a first plurality of channel layers 22B (Annotated Fig. 28C & ¶ 29, nanostructures 22B are channels; see Fig. 24B for the corresponding structures);
a second nanosheet structure STK (Annotated Fig. 28C, ¶ 29, ¶ 33, ¶ 50, ¶ 56, ¶ 1 & claim 6 disclose the right stack STK of FinFet 196 is a nano sheet structure) comprising a second plurality of gate structures 68 (Annotated Fig. 28C, ¶ 36 & ¶ 50, gate electrodes 68 of FinFET 196 (corresponding to GAA transistor 96 in Fig. 24B)) alternately stacked with a second plurality of channel layers 22B (Annotated Fig. 28C & ¶ 29, nanostructures 22B are channels; see Fig. 24B for the corresponding structures); and
at least one epitaxial source/drain region 148 (Fig. 28C, ¶ 50, ¶ 56, abstract & claim 1, source/drain region 148 is an epitaxy source/drain region) disposed between the first and second nanosheet structures STK (Annotated Fig. 28C); and
a dielectric layer 180 (Fig. 28C, ¶ 53 & ¶ 42, dielectric layer 180) disposed in a trench 78 (Figs. 16B, 17B, Annotated Fig. 28C & ¶ 39, trench 78 is the space within the region 148 that accommodates the dielectric layer 180) in the at least one epitaxial source/drain region 148.
Regarding claim 14, Lin in Fig. 28C further teaches the dielectric layer 180 comprises one of a material with a negative coefficient of thermal expansion and a material with a positive coefficient of thermal expansion (¶ 53 & ¶ 42, the dielectric layer 180 includes silicon nitride, which is the same positive CTE dielectric material as the Applicant purported in paragraph 63 in the specification of the present application).
Regarding claim 15, Lin in Figs. 28C further teaches the dielectric layer 180 is disposed on a first side (Fig. 28C, inner left side) of the at least one epitaxial source/drain region 148.
Regarding claim 16, Lin in Fig. 28C further teaches a source/drain contact 194 (Fig. 28C & ¶ 51, source/drain contact plugs 194) disposed on a second side (Fig. 28C, inner right side) of the at least one epitaxial source/drain region 148, wherein the second side is opposite the first side (Fig. 28C, the inner left side and the inner right side of the region 148 are opposite to each other).
Regarding independent claim 18, Lin in Figs. 28C and Annotated Fig. 28C teaches a semiconductor device (Fig. 28C) comprising:
a first epitaxial source/drain region 148 (Fig. 28C, ¶ 50, ¶ 56, abstract & claim 1, the rightmost source/drain region 148 is an epitaxy source/drain region) corresponding to a first transistor 196 (Fig. 28C & ¶ 50, the rightmost FinFet 196);
a second epitaxial source/drain region 148 (Fig. 28C, ¶ 50, ¶ 56, abstract & claim 1, the center source/drain region 148 is an epitaxy source/drain region) corresponding to a second transistor 196 (Fig. 28C & ¶ 50, the center FinFet 196);
a first dielectric layer 180 (Fig. 28C, ¶ 53 & ¶ 42, dielectric layer 180) disposed in a first trench 78 (Figs. 16B, 17B, Annotated Fig. 28C & ¶ 39, trench 78 is the space within the region 148 that accommodates the dielectric layer 180) in the first epitaxial source/drain region 148; and
a second dielectric layer 78 (Figs. 16B, 17B, Annotated Fig. 28C & ¶ 39, trench 78 is the space within the region 148 that accommodates the dielectric layer 180) disposed in a second trench 78 (Figs. 16B, 17B, Annotated Fig. 28C & ¶ 39, trench 78 is the space within the region 148 that accommodates the dielectric layer 180) in the second epitaxial source/drain region 148;
wherein the first trench 78 is disposed on a first side (Fig. 28C, left side) of the semiconductor device and the second trench 78 is disposed on a second side (Fig. 28C, right side) of the semiconductor device opposite the first side (Fig. 28C, the left side and the right side of the semiconductor device are opposite to each other).
Regarding claim 19, Lin in Fig. 28C further teaches the first dielectric layer 180 and second dielectric layer 180 each comprise one of a material with a negative coefficient of thermal expansion and a material with a positive coefficient of thermal expansion (¶ 53 & ¶ 42, the dielectric layer 180 includes silicon nitride, which is the same positive CTE dielectric material as the Applicant purported in paragraph 63 in the specification of the present application).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of US 2008/0230773 A1 to Dickey et al. (“Dickey”).
Regarding claim 3, Lin in Fig. 28C teaches the at least one epitaxial source/drain region 148 corresponds to a p-type transistor (¶ 29).
Lin further discloses the dielectric layer 180 includes silicon nitride (¶ 53 & ¶ 42).
However, Lin does not explicitly disclose the dielectric layer comprises a material with a negative coefficient of thermal expansion.
Dickey teaches that a dielectric can be made from silicon nitride or zeolites (¶ 101). In other words, Dickey recognizes that silicon nitride and zeolites are functional equivalent as being able to function as dielectric materials.
According to Section 2144.06.II, "In order to rely on equivalence as a rationale supporting an obviousness rejection, the equivalency must be recognized in the prior art" In re Ruff, 256 F.2d 590, 118 USPQ 340 (CCPA 1958). The Section 2144.06.II further states that "An express suggestion to substitute one equivalent component or process for another is not necessary to render such substitution obvious. In re Fout, 675 F.2d 297, 213 USPQ 532 (CCPA 1982).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to substitute silicon nitride taught by Lin with another functionally-equivalent zeolites taught by Dickey. Since zeolites is the same negative CTE dielectric material as the Applicant purported in paragraph 63 in the specification of the present application, the combination of Lin and Dickey teaches the dielectric layer comprises a material with a negative coefficient of thermal expansion.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of US 2022/0254925 A1 to Gardner et al. (“Gardner”).
Regarding claim 17, Lin does not explicitly disclose the source/drain contact is connected to a backside power delivery network.
Gardner recognizes a need for providing delivery of power to a transistor device (¶ 56). Gardner satisfies the need by providing a source/drain contact (¶ 56, conductive structures for connecting S/d regions to a backside power delivery network) connected to a backside power delivery network (¶ 56, backside power delivery network (BSPDN)).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to combine the source/drain contact taught by Lin with the backside power delivery network taught by Gardner, so as to provide delivery of power to a transistor device (Gardner: ¶ 56).
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Claims 7, 12 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if (i) rewritten in independent form to include all of the limitations of the base claim and any intervening claims or (ii) the objected claim and any intervening claims are fully incorporated into the base claim, AND if any claim objections set forth in this Office action is overcome.
Claim 7 would be allowable, because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 7, wherein the first side corresponds to one of a frontside and a backside of the semiconductor device.
Claim 12 would be allowable, because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 12, wherein part of the dielectric layer is disposed through a semiconductor layer, the semiconductor layer contacting a surface of the at least one epitaxial source/drain region.
Claim 20 would be allowable, because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 20, a first source/drain contact disposed on the first epitaxial source/drain region on the second side of the semiconductor device; and a second source/drain contact disposed on the second epitaxial source/drain region on the first side of the semiconductor device.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 10,879,308 B1 to Ando et al.
US 2023/0253478 A1 to Wong et al.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIKKA LIU whose telephone number is (571)272-2568. The examiner can normally be reached on 9AM-5AM EST M-F.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached on 571-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/M.L./Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817