DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In response to an Office action mailed on 02/18/2026 (“02/18/2026 OA”), the Applicant amended independent claims 1, 13 and 18 in a reply filed on 05/18/2026. Applicant’s amendments to independent claims 1, 13 and 8 have substantively changed the scope of claims 1, 13 and 18 as well as their respective dependent claims.
Currently, claims 1-20 are examined as below.
Response to Arguments
Applicant’s amendments to claim 12 have overcome the claim objections as set forth under line item number 1 in the 02/18/2026 OA.
Applicant’s amendments to independent claims 1, 13 and 18 have overcome the prior-art rejections as set forth under line item numbers 2-4 in the 02/18/2026 OA.
New reference is introduced. New grounds of rejections under 35 U.S.C. 102(a)(2) and 103 are provided as follows.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2 and 4-11 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2025/0087578 A1 to Chen et al. (“Chen”).
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Regarding independent claim 1, Chen in Figs. 3, 14 and 16-18 teaches a semiconductor device (abstract & ¶ 64, semiconductor device) comprising:
at least one epitaxial source/drain region 48 (Figs. 14, 18, ¶ 20, epitaxial source/drain region 48); and
a dielectric layer 80 (Figs. 14, 18, ¶ 28, isolation layer 80, and at least a part of the layer 80 is within the region 48) disposed in a trench 78 (Figs. 3, 14, 18, ¶ 26, trench 78) in the at least one epitaxial source/drain region 48;
wherein the dielectric layer 80 is disposed adjacent to the at least one epitaxial source/drain region 48 corresponding to a frontside of the semiconductor device (Figs. 18, ¶ 58, since the structure formed in Figs. 16-18 corresponds to a back-side (i.e. upper side) of the semiconductor device, the layer 80 is formed in Fig. 14 corresponds to a frontside (i.e., lower side in Fig. 18) of the semiconductor device).
Regarding claim 2, Chen in Fig. 18 further teaches the dielectric layer 80 comprises a material with a positive coefficient of thermal expansion (¶ 28, the layer 80 includes silicon nitride or silicon oxide, which is the same dielectric material having a positive CTE as the Applicant purported in paragraph 63 in the specification of the present application).
Regarding claim 4, Chen in Fig. 18 further teaches the at least one epitaxial source/drain region 48 corresponds to an n-type transistor (¶ 20, n-type transistor) and the dielectric layer 80 comprises a material with a positive coefficient of thermal expansion (¶ 28, the layer 80 includes silicon nitride or silicon oxide, which is the same dielectric material having a positive CTE as the Applicant purported in paragraph 63 in the specification of the present application).
Regarding claim 5, Chen in Fig. 18 further teaches the dielectric layer 80 is disposed on a first side (Fig. 18, inner left side) of the at least one epitaxial source/drain region 48.
Regarding claim 6, Chen in Fig. 18 further teaches a source/drain contact 94 (Fig. 18, ¶ 24, source/drain contact plug 94) disposed on a second side (Fig. 18, inner right side) of the at least one epitaxial source/drain region 48, wherein the second side is opposite the first side (Fig. 18).
Regarding claim 7, Chen in Fig. 18 further teaches the first side (Fig. 18, inner left side of region 48, and the region 48 corresponds to the lower side of Fig. 18) corresponds to the frontside of the semiconductor device (Fig. 18, ¶ 58, the lower side of Fig. 18 is the frontside of the semiconductor device; see the rejection of claim 1 as noted above).
Regarding claim 8, Chen in Figs. 3 and 18 further teaches a first portion (Figs. 3, 18) of the trench 78 is disposed in the at least one epitaxial source/drain region 48 and a second portion (Figs. 3, 18) of the trench 78 is disposed in an additional dielectric layer 52 (¶ 22, inter-layer dielectric (ILD) layer 52) on the at least one epitaxial source/drain region 48 (Figs. 3, 18).
Regarding claim 9, Chen in Figs. 3-4 and 18 further teaches a first portion of the dielectric layer 80 is disposed in the first portion of the trench 78 (Figs. 3-4, 18) and a second portion of the dielectric layer 80 is disposed in the second portion of the trench 78 (Figs. 3-4, 18).
Regarding claim 10, Chen in Fig. 18 further teaches a spacer layer 50 (Fig. 18, ¶ 22, CESL 50 keeps the layer 52 spaced apart from the layer 38) disposed adjacent the second portion of the dielectric layer 80.
Regarding claim 11, Chen in Figs. 14 and 18 further teaches a stacked structure 68, 22B (Figs. 14, 18) comprising a plurality of gate structures 68 (Figs. 14, 18, ¶ 24, gate electrodes 68) alternately stacked with a plurality of channel layers 22B (Figs. 14, 18, ¶ 20, semiconductor layers 22B are used as channels of GAA transistors), wherein the at least one epitaxial source/drain region 48 is disposed on a side of the stacked structure 68, 22B (Figs. 14, 18).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of US 2008/0230773 A1 to Dickey et al. (“Dickey”).
Regarding claim 3, Chen in Fig. 18 teaches the at least one epitaxial source/drain region 48 corresponds to a p-type transistor (¶ 20, p-type transistor).
Chen further discloses the dielectric layer 80 includes silicon nitride (¶ 28).
Chen does not explicitly disclose the dielectric layer comprises a material with a negative coefficient of thermal expansion.
Dickey teaches that a dielectric can be made from silicon nitride or zeolites (¶ 101). In other words, Dickey recognizes that silicon nitride and zeolites are functional equivalent as being able to function as dielectric materials.
According to Section 2144.06.II, "In order to rely on equivalence as a rationale supporting an obviousness rejection, the equivalency must be recognized in the prior art" In re Ruff, 256 F.2d 590, 118 USPQ 340 (CCPA 1958). The Section 2144.06.II further states that "An express suggestion to substitute one equivalent component or process for another is not necessary to render such substitution obvious. In re Fout, 675 F.2d 297, 213 USPQ 532 (CCPA 1982).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to substitute silicon nitride taught by Chen with another functionally-equivalent zeolites taught by Dickey. Since zeolites is the same negative CTE dielectric material as the Applicant purported in paragraph 63 in the specification of the present application, the combination of Chen and Dickey teaches the dielectric layer comprises a material with a negative coefficient of thermal expansion.
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Claim 12 is objected to as being dependent upon a rejected base claim, but would be allowable if (i) rewritten in independent form to include all of the limitations of the base claim and any intervening claims or (ii) the objected claim and any intervening claims are fully incorporated into the base claim.
Claim 12 would be allowable, because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 12, wherein a part of the dielectric layer is disposed through a semiconductor layer, the semiconductor layer contacting a surface of the at least one epitaxial source/drain region.
Claims 13-20 are allowed.
Regarding independent claim 13, Chen in Figs. 3, 14 and 18 teaches a semiconductor device (abstract & ¶ 64, semiconductor device) comprising:
a first nanosheet structure 96 (Fig. 14, ¶ 10, ¶ 20, ¶ 42, the leftmost transistor 96 including nanostructures (i.e., nanosheet structures) 22B) comprising a first plurality of gate structures 68 (¶ 24, gate electrodes 68) alternately stacked with a first plurality of channel layers 22B (¶ 20, nanostructures 22B are channels);
a second nanosheet structure 96 (Fig. 14, ¶ 10, ¶ 20, ¶ 42, the center transistor 96 including nanostructures (i.e., nanosheet structures) 22B) comprising a second plurality of gate structures 68 (¶ 24, gate electrodes 68) alternately stacked with a second plurality of channel layers 22B (¶ 20, nanostructures 22B are channels); and
at least one epitaxial source/drain region 48 (Figs. 14, 18, ¶ 20, epitaxial source/drain region 48) disposed between the first and second nanosheet structures 96; and
a dielectric layer 80 (Figs. 14, 18, ¶ 28, isolation layer 80, and at least a part of the layer 80 is within the region 48) disposed in a trench 78 (Figs. 3, 14, 18, ¶ 26, trench 78) in the at least one epitaxial source/drain region 48.
However, the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 13, wherein a part of the dielectric layer is disposed through a semiconductor layer, the semiconductor layer contacting a surface of the at least one epitaxial source/drain region.
Therefore, independent claim 13 is allowed.
Claims 14-17 are allowed, because they depend from the allowed claim 13.
Regarding independent claim 18, Chen in Figs. 3, 14 and 16-18 teaches a semiconductor device (abstract & ¶ 64, semiconductor device) comprising:
a first epitaxial source/drain region 48 (Fig. 14, ¶ 20, the leftmost epitaxial source/drain region 48) corresponding to a first transistor 96 (Fig. 14, ¶ 42, transistor 96);
a second epitaxial source/drain region 48 (Fig. 14, ¶ 20, the rightmost epitaxial source/drain region 48) corresponding to a second transistor 96 (Fig. 14, ¶ 42, transistor 96);
a first dielectric layer 80 (Figs. 14, 18, ¶ 28, isolation layer 80, and at least a part of the layer 80 is within the region 48) disposed in a first trench 78 (Figs. 3, 14, ¶ 26, the leftmost trench 78) in the first epitaxial source/drain region 48;
a second dielectric layer 80 (Figs. 14, 18, ¶ 28, isolation layer 80, and at least a part of the layer 80 is within the region 48) disposed in a second trench 78 (Figs. 3, 14, ¶ 26, the rightmost trench 78) in the second epitaxial source/drain region 48,
wherein the first trench 78 is disposed on a first side of the semiconductor device (Fig. 14, left side of the device) and the second trench 78 is disposed on a second side of the semiconductor device (Fig. 14, right side of the device) opposite the first side.
However, the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 18, a source/drain contact disposed on the first epitaxial source/drain region on the second side of the semiconductor device.
Therefore, independent claim 18 is allowed.
Claims 19-20 are allowed, because they depend from the allowed claim 18.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIKKA LIU whose telephone number is (571)272-2568. The examiner can normally be reached on 9AM-5AM EST M-F.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached on 571-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/M.L./Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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