Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the filing of the Applicant Arguments/Remarks Made in an Amendment on 01/21/2026. Currently, claims 1-20 are pending in the application. Claims 17-20 have been added new.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5 and 8-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Toyama et al (US 20170179026 A1).
Regarding claim 1, Figures 1-16 of Toyama disclose a semiconductor device comprising:
a first gate structure (between 11-170) including a first step structure extending in a first direction (horizontal in the Figures), wherein the first step structure includes first gate lines (146, Figure 15C) stacked in a stair shape;
an insulating layer (170, [0180])) disposed on the first step structure;
a second gate structure (between 180-270) disposed on the first gate structure and including a second step structure extending in the first direction (horizontal in the Figures), wherein the second step structure includes second gate lines (246, Figure 15C, [0228]) stacked in a stair shape;
a channel structure (60 in 55, [0203] and [0211], Figure 16C) extending through the first gate structure and the second gate structure, the channel structure having a first width;
a first support (171, [0182]) extending through the insulating layer (170) and the first step structure, the first support having a second width that is greater than the first width (please see the Figure 14B, the width of 171 is greater than channel forming pillar 55); and
a second support (171+271, [0197]) extending through the second step structure and the first gate structure, the second support having a third width that is greater than the first width (please see Figure 10B, 271 is wider than 55).
Regarding claim 2, Figures 1-16 of Toyama disclose that the semiconductor device of claim 1, wherein the first width is a width of a top surface of the channel structure (55), the second width is a width of a top surface of the first support (171), and the third width is a width of a top surface of the second support (171+271).
Regarding claim 3, Figures 1-16 of Toyama disclose that the semiconductor device of claim 1, wherein the first step structure (between 11 and 170) and the second step structure (between 180-270) are adjacent to each other in a second direction (vertical direction in the Figure) crossing the first direction.
Regarding claim 4, Figures 1-16 of Toyama disclose that the semiconductor device of claim 1, wherein the first step structure (between 11 and 170) and the second step structure (between 180-270) are aligned in the second direction (vertical direction in the Figure).
Regarding claim 5, Figures 1-16 of Toyama disclose that the semiconductor device of claim 1, further comprising: first contact plugs (86, in region 171, [0239], Figure 16B) positioned between adjacent first supports and connected to the first gate lines, respectively; and second contact plugs (86, in region 271, [0239]) positioned between adjacent second supports and connected to the second gate lines, respectively.
Regarding claim 8, Figures 1-16 of Toyama disclose that the semiconductor device of claim 1, wherein the channel structure (60) and the second support (171+271) include a stepped sidewall, and the first support (171) includes a non-stepped sidewall.
Regarding claim 9, Figures 1-16 of Toyama disclose that the semiconductor device of claim 1, wherein the second width is greater than the third width (considering the width of 171 at the topmost region and the width of 171+271 at the narrowest region meets the limitation since the claim does not specify where to measure the width).
Regarding claim 10, Figures 1-16 of Toyama disclose that the semiconductor device of claim 1, further comprising: a third support (consider one of the 171+271) positioned between the channel structure (60) and the first support (171), extending through the second gate structure and the first gate structure, and having a fourth width greater than the first width and less than the second width (considering the width of 171+271 at the topmost region, and width of 60 at a narrow region and width of 171 at the narrowest region meets the limitation since the claim does not specify the region where to take the width).
Regarding claim 11, Figures 1-16 of Toyama disclose that the semiconductor device of claim 1, wherein at least one of the first support (171) and the second support (171+271) includes a dummy channel layer ([0203], 171 having dummy memory stack which includes channel).
Regarding claim 12, Figures 1-16 of Toyama disclose a semiconductor device comprising:
a first gate structure (between 11 and 170, Figure 16C) including a first step structure extending in a first direction (horizontal in the Figures), wherein the first step structure includes first gate lines (146, [0228]) stacked in a stair shape;
an insulating layer (170, [0180]) disposed on the first step structure;
a second gate structure (between 180 and 270) disposed on the first gate structure and including a second step structure extending in the first direction (horizontal in the Figures), wherein the second step structure includes second gate lines (246, [0228]) stacked in a stair shape;
an etch stop layer (180, [0183]) positioned between the first gate structure and the second gate structure;
a channel structure (60 in 55, [0203]) extending through the first gate structure, the etch stop layer (180), and the second gate structure, and including a stepped sidewall (at 170+180);
a first support (171, [0182]) extending through the insulating layer (170) and the first step structure and including a non-stepped sidewall; and
a second support (171+271) extending through the second step structure (between 180 and 270), the etch stop layer (180), and the first gate structure (between 11 and 270).
Regarding claim 13, Figures 1-16 of Toyama disclose that the semiconductor device of claim 12, wherein the first step structure (between 11-170) and the second step structure (between 180-270) are aligned in a second direction (vertical direction) crossing the first direction.
Regarding claims 14-15, Figures 1-16 of Toyama disclose that the semiconductor device of claim 12, wherein the channel structure has a first width, the first support has a second width greater than the first width, and the second support has a third width greater than the first width (width of 171 and 172 are greater than 55, please see Figure 16B), wherein the first width is a width of a top surface of the channel structure, the second width is a width of a top surface of the first support, and the third width is a width of a top surface of the second support.
Regarding claim 16, Figures 1-16 of Toyama disclose that the semiconductor device of claim 14, wherein the second width is greater than the third width (when considering the width of 171 at the topmost section and width of 171+271 at the narrowest section meets the limitation since the claim does not specify where to measure the width).
Regarding claims 17-18, Figures 1-16 of Toyama disclose that the semiconductor device of claim 1, wherein the insulating layer (170) and the second step structure (between 180-270) are adjacent in a second direction (vertical direction) crossing the first direction (horizontal direction) at substantially the same level.
Regarding claim 19, Figures 1-16 of Toyama disclose a semiconductor device comprising:
a first gate structure (between 11-170) including a cell region (100), a first contact region (region 86 for connecting 146) and a second contact region (region 86 for connecting 246), wherein the cell region is adjacent to the first and second contact regions in a first direction (horizontal direction in the Figueres 16), the first contact region is adjacent to the second contact region in a second direction (vertical direction in Figure 16) crossing the first direction, and the first gate structure includes a first step structure (at 146) at the first contact region;
an insulating layer (170) disposed on the first step structure at the first contact region (86 connecting 146);
a second gate structure (between 180-270) disposed on the cell region and the second contact region (of 86 for connecting 246) of the first gate structure and including a second step structure (of 246) at the second contact region;
a first dummy channel structure (171 having dummy memory channel, [0203]) extending through the insulating layer (170) and the first step structure at the first contact region; and
a second dummy channel structure (171+271) extending through the second step structure and the first gate structure at the second contact region (region 86 connecting lines 246).
Regarding claim 20, Figures 1-16 of Toyama disclose that the semiconductor device of claim 19, further comprising: a channel structure (60 in 55, [0203]) extending through the first gate structure and the second gate structure at the cell region (100);
a first support (171) extending through the insulating layer and the first step structure; and
a second support (171+172) extending through the second step structure and the first gate structure, wherein the channel structure includes a stepped sidewall, and the first support and the second support include a non-stepped sidewall.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-7 are rejected under 35 U.S.C. 103 as being obvious over Toyama et al (US 20170179026 A1) in view of KIM et al (US 20180102314 A1).
Regarding claims 6-7, Figures 1-16 of Toyama disclose that the semiconductor device of claim 1, wherein the channel structure (60, [0203]) includes a stepped sidewall (in region of 180), wherein the stepped sidewall of the channel structure includes a step difference positioned between the first gate structure and the second gate structure.
Toyama does not teach that the first support and the second support include a non-stepped sidewall.
However, KIM is a pertinent art which teaches a three-dimensional semiconductor memory device that includes memory cells arranged in a three-dimensional structure. Figure 1 of KIM teaches support structure (SP, [0029]) having non-stepped sidewall.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the first support and the second support having a non-stepped sidewall according to the teaching of KIM in order to create uniform support structure as a matter of design choice and manufacturing ease. Further, it has been held that the configuration of the container (support structure sidewalls in this case) was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular shape of the claimed container (support structure sidewalls in this case) was significant, In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Response to Arguments
Applicant's arguments filed on 01/21/2026 have been fully considered but they are not persuasive.
Applicant’s main argument include: Figures 1-16 of Toyama do not teach the amended claims 1 and 12.
In response, the Examiner respectfully points out that “A prior art reference must be considered in its entirety, i.e., as a whole, including portions that would lead away from the claimed invention, MPEP § 2141.02. Figures 1-16 of Toyama teach the amended limitation as explained above on a broadest reasonable interpretation.
Examiner Notes
A reference to specific paragraphs, columns, pages, or figures in a cited prior art reference is not limited to preferred embodiments or any specific examples. It is well settled that a prior art reference, in its entirety, must be considered for all that it expressly teaches and fairly suggests to one having ordinary skill in the art. Stated differently, a prior art disclosure reading on a limitation of Applicant's claim cannot be ignored on the ground that other embodiments disclosed were instead cited. Therefore, the Examiner's citation to a specific portion of a single prior art reference is not intended to exclusively dictate, but rather, to demonstrate an exemplary disclosure commensurate with the specific limitations being addressed. In re Heck, 699 F.2d 1331, 1332-33,216 USPQ 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 USPQ 275, 277 (CCPA 1968)). In re: Upsher-Smith Labs. v. Pamlab, LLC, 412 F.3d 1319, 1323, 75 USPQ2d 1213, 1215 (Fed. Cir. 2005); In re Fritch, 972 F.2d 1260, 1264, 23 USPQ2d 1780, 1782 (Fed. Cir. 1992); Merck& Co. v. BiocraftLabs., Inc., 874 F.2d 804, 807, 10 USPQ2d 1843, 1846 (Fed. Cir. 1989); In re Fracalossi, 681 F.2d 792,794 n.1, 215 USPQ 569, 570 n.1 (CCPA 1982); In re Lamberti, 545 F.2d 747, 750, 192 USPQ 278, 280 (CCPA 1976); In re Bozek, 416 F.2d 1385, 1390, 163 USPQ 545, 549 (CCPA 1969).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAJA AHMAD whose telephone number is (571)270-7991. The examiner can normally be reached on Monday to Friday from 8:00 AM to 5:00 PM (Eastern Time).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, GAUTHIER STEVEN B, can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHAJA AHMAD/
Primary Examiner, Art Unit 2813