DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zundel et al. (US 2020/0357917 A1 hereinafter referred to as “Zundel”).
With respect to claim 1, Zundel discloses, in Figs.1A-9, a semiconductor device, comprising: a semiconductor substrate (106); a semiconductor layer (114)/(108) formed on the semiconductor substrate (106) and including a peripheral region/(region of metallization 124b surrounding active area) and an active region (102) surrounded by the peripheral region (102) in plan view (see Par.[0030] wherein each active cell area 102 of the power semiconductor device includes a plurality of parallel gate trenches 104 formed in a semiconductor substrate 106, with a semiconductor mesa region 108 between adjacent ones of the parallel gate trenches 104; a source region 110 of a first conductivity type and a body region 112 of a second conductivity type are formed in each semiconductor mesa region 108; a drift region 114 of the first conductivity type is formed below the body region 112; see Par.[0029] wherein the power semiconductor device 100 includes a plurality of active cell areas 102; the active cell areas 102 are illustrated as rectangles with thin dashed lines in FIG. 1A; the term ‘active cell area’ as used herein refers to a region of the power semiconductor device which carries part of the load current of the device during device operation); sets of gate trenches (104) formed in the semiconductor layer (108), the plural sets/(gate trenches in directions E1-E4 in each part 132) of gate trenches (104) including a first set and a second set (see Par.[0037]-[0038] wherein he first group of parallel gate trenches 104 extends lengthwise in parallel in a first direction E1, the second group of parallel gate trenches 104 extends lengthwise in parallel in a second direction E2, the third group of parallel gate trenches 104 extends lengthwise in parallel in a third direction E3, and the fourth group of parallel gate trenches 104 extends lengthwise in parallel in a fourth direction E4); gate electrodes (116), each embedded in a corresponding one of the gate trenches (104) in the plural sets (132a) of gate trenches (104) (see Par.[0039]-[0040] wherein for the upper-left quadrant of gate trench groups, the gate electrodes 116 of the group of parallel gate trenches 104 having the lengthwise extension direction E1 are electrically connected at the same end to a first branch 124b_1 of the gate contact structure 124b which extends lengthwise in a direction orthogonal to E1; the gate electrodes 116 of the group of parallel gate trenches 104 having the lengthwise extension direction E2 are electrically connected at the same end to a second branch 124b_2 of the gate contact structure 124b which extends lengthwise in a direction orthogonal to E2; the gate electrodes 116 of the group of parallel gate trenches 104 having the lengthwise extension direction E3 are electrically connected at the same end to a third branch 124b_3 of the gate contact structure 124 which extends lengthwise in a direction orthogonal to E3; the gate electrodes 116 of the group of parallel gate trenches 104 having the lengthwise extension direction E4 are electrically connected at the same end to a fourth branch 124b_4 of the gate contact structure 124b which extends lengthwise in a direction orthogonal to E4); field plate electrodes (118), each embedded in a corresponding one of the gate trenches (104) of the plural sets of gate trenches in a state insulated from the gate electrode (116) (see Par.[0030] wherein the gate electrodes 116 are electrically insulated from the semiconductor substrate 106 by a gate dielectric 120, and the field electrodes 118 are electrically insulated from the semiconductor substrate 106 and from the gate electrodes 116 by a field dielectric 122 which is typically thicker than the gate dielectric 120); an insulation layer (120) formed on the semiconductor layer (108); a gate interconnection (124b) formed on the insulation layer (102) and connected to the gate electrodes (116), the gate interconnection including a peripheral gate interconnection portion (124b_1), located in the peripheral region in plan view, and an inner gate interconnection portion (124b_3), located in the active region in plan view; and a source interconnection (124a) formed on the insulation layer (120) and separated from the gate interconnection (124b), wherein: each of the field plate electrodes (118) includes two ends connected to the source interconnection (124a) (see Par.[0034]-[0035] wherein a second metallization layer 132 overlying the first metallization layer 124 is in contact with the source contact structure 124a to form source/body contact pads 132a which are electrically connected to the source region 110, the body region 112 and the field electrodes 118 of the active cell areas 102 through the first part 124a of the first metallization layer 124. An insulating material 134 such as imide, e.g., separates the second metallization layer 132 from the second part 124b of the first metallization layer 124 to prevent shorting between the source contact structure 124a and the gate contact structure 124b which are formed in the first metallization layer 124); the peripheral gate interconnection portion (124b_1) includes a first gate finger (124b_2) extending in a first direction in plan view, and the inner gate interconnection portion (124b_3) includes a second gate finger (124b_2) extending in a second direction orthogonal to the first direction in plan view; each gate trench (104) of the first set extends in the first direction in plan view and intersects the second gate finger (124b_2); and each gate trench (104) of the second set extends in the second direction in plan view and intersects the first gate finger (124b_2) (see Par.[0039]-[0046] wherein as shown in Fig.2 two branches 124b_2 separated by metal bridges are directly connected to 124b_1 and 124b_3; the quadrants of gate trenches 104 are electrically connected to one another by metal bridges 202 which extend through breaks in the branches 124b_2, 124b_3 of the gate contact structure 124b positioned between adjacent quadrants of gate trenches 104).
With respect to claim 2, Zundel discloses, in Figs.1A-9, the semiconductor device, wherein: each gate trench (104) of the first set intersects the second gate finger (124b_2) between the two ends of the field plate electrode (118) embedded in the gate trench (104) in plan view; and each gate trench (104) of the second set intersects the first gate finger (124b_2) between the two ends of the field plate electrode (118) embedded in the gate trench in plan view (see, for example, Fig.1A).
With respect to claim 3, Zundel discloses, in Figs.1A-9, the semiconductor device, wherein the source interconnection includes: a peripheral source interconnection portion (124a_1-124a_4) located in the peripheral region; and an inner source interconnection portion (124a_1-124a_4) located in the active region (see, for example, Fig.1A; see Par.[0045]-[0047] wherein electrically connecting the source contact structures 124a_1, 124a_2, 124a_3, 124a_4 using the metal bridges 202 formed in the first metallization layer 124 protects against gate oxide damage and avoids yield loss during testing of the power semiconductor device 200. During use of the device 200, electrically connecting the source contact structures 124a_1, 124a_2, 124a_3, 124a_4 using the metal bridges 202 formed in the first metallization layer 124 may provide protection, e.g., in the case of separate bond wire connections to each source/body contact pad 132a formed in the second metallization layer 132).
With respect to claim 4, Zundel discloses, in Figs.1A-9, the semiconductor device, wherein: each gate trench of the first set is entirely located inside the active region; each gate trench of the second set extends across the active region and the peripheral region; the two ends of the field plate electrode embedded in each gate trench of the first set are both connected to the inner source interconnection portion; and one of the two ends of the field plate electrode embedded in each gate trench of the second set is connected to the inner source interconnection portion, and the other one of the two ends is connected to the peripheral source interconnection portion (see Par.[0039]-[0040] wherein for the upper-left quadrant of gate trench groups, the gate electrodes 116 of the group of parallel gate trenches 104 having the lengthwise extension direction E1 are electrically connected at the same end to a first branch 124b_1 of the gate contact structure 124b which extends lengthwise in a direction orthogonal to E1; the gate electrodes 116 of the group of parallel gate trenches 104 having the lengthwise extension direction E2 are electrically connected at the same end to a second branch 124b_2 of the gate contact structure 124b which extends lengthwise in a direction orthogonal to E2; the gate electrodes 116 of the group of parallel gate trenches 104 having the lengthwise extension direction E3 are electrically connected at the same end to a third branch 124b_3 of the gate contact structure 124 which extends lengthwise in a direction orthogonal to E3; the gate electrodes 116 of the group of parallel gate trenches 104 having the lengthwise extension direction E4 are electrically connected at the same end to a fourth branch 124b_4 of the gate contact structure 124b which extends lengthwise in a direction orthogonal to E4).
With respect to claim 5, Zundel discloses, in Figs.1A-9, the semiconductor device, wherein: the gate electrode embedded in each gate trench of the first set is electrically connected to the second gate finger in a region where the gate trench of the first set intersects the second gate finger in plan view; and the gate electrode embedded in each gate trench of the second set is electrically connected to the first gate finger in a region where the gate trench of the second set intersects the first gate finger in plan view (see, for example, Fig.1A).
With respect to claim 6, Zundel discloses, in Figs.1A-9, the semiconductor device, wherein the second gate finger intersects two or more sets of gate trenches including the gate trenches of the first set.
With respect to claim 7, Zundel discloses, in Figs.1A-9, the semiconductor device, wherein the inner gate interconnection portion further includes at least one other gate finger intersecting the second gate finger in plan view.
With respect to claim 8, Zundel discloses, in Figs.1A-9, the semiconductor device, wherein the at least one other gate finger includes a gate finger extending in the first direction in plan view.
With respect to claim 9, Zundel discloses, in Figs.1A-9, the semiconductor device, wherein the at least one other gate finger includes two gate fingers extending in the first direction in plan view.
With respect to claim 10, Zundel discloses, in Figs.1A-9, the semiconductor device, wherein the inner gate interconnection portion further includes a third gate finger forming a T-shaped junction with the second gate finger in plan view.
With respect to claim 11, Zundel discloses, in Figs.1A-9, the semiconductor device, wherein the peripheral gate interconnection portion further includes a fourth gate finger extending in the second direction in plan view.
With respect to claim 12, Zundel discloses, in Figs.1A-9, the semiconductor device, wherein the plural sets of gate trenches each include gate trenches arranged parallel to one another at equal intervals.
With respect to claim 13, Zundel discloses, in Figs.1A-9, the semiconductor device, further comprising: a pair of first linking trenches/(gates trenches crossing 124b_4) extending in the second direction in plan view and linking the gate trenches of the first set to each other; and a pair of second linking trenches/(gates trenches crossing 124b_1) extending in the first direction in plan view and linking the gate trenches of the second set to each other, wherein: the field plate electrodes embedded in the gate trenches of the first set are connected to each other in the pair of first linking trenches; the field plate electrodes (118) embedded in the gate trenches of the second set are connected to each other in the pair of second linking trenches; and the two ends of each of the field plate electrodes are connected to another field plate electrode.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Zundel in view of Shinoda et al. (US 2021/0367071 A1 hereinafter referred to as “Shinoda”).
With respect to claim 14, Zundel discloses all the claimed limitation of claim 1. Zundel does not explicitly disclose all the limitations of claim 14.
Shinoda discloses, in Figs.1-16, the semiconductor device, wherein: the semiconductor substrate includes a surface on which the semiconductor layer (7-8) is formed, the surface including a first side extending in the first direction/(y-direction) and a second side extending in the second direction/(Z-direction); each gate trench (34) of the first set has a length (W1) of 1/2 or less of a dimension of the first side; and each gate trench (34) of the second set has a length (D) of 1/2 or less of a dimension of the second side (see Par.[0051]-[0052] wherein the trench width W may be 0.5 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, or 2 μm or more and 3 μm or less. The trench width W may be 0.5 μm or more and 2 μm or less; the trench depth D may be 1 μm or more and 10 μm or less; the trench depth D may be 1 μm or more and 2.5 μm or less, 2.5 μm or more and 5 μm or less, 5 μm or more and 7.5 μm or less, or 7.5 μm or more and 10 μm or less; the trench depth D may be 2 μm or more and 6 μm or less; an aspect ratio D/W of the trench 25 may exceed 1 and may be 5 or less. The aspect ratio D/W is a ratio of the trench depth D to the trench width W. Specifically, the aspect ratio D/W may be 2 or more).
Zundel and Shinoda are analogous art because they are all directed to a semiconductor device, and one of ordinary skill in the art would have had a reasonable expectation of success by modifying Zundel to include Shinoda because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to modify gate trench dimensions in Zundel by including specific dimension to defined field pate and gate electrode as taught by Shinoda in order to ratio in dimensions so as to define the field plate electrode is buried on a bottom wall side in the gate trench thereby provide a semiconductor device capable of shortening a switching descent time while suppressing an increase in power consumption in a structure including a field effect transistor including a plurality of unit cells.
With respect to claim 15, Shinoda discloses, in Figs.1-16, the semiconductor device, wherein each gate trench of the first set has a length of 1/3 or less of the dimension of the first side.
Citation of Pertinent Prior Art
The prior art made of record (e.g.; see PTO-892) and not relied upon is considered pertinent to applicant's disclosure.
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOULOUCOULAYE INOUSSA whose telephone number is (571)272-0596. The examiner can normally be reached Monday-Friday (10-18).
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/Mouloucoulaye Inoussa/ Primary Examiner, Art Unit 2818