DETAILED ACTION
Claims 21-31 have been presented and examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of a prior-filed application (15/031,285) under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged.
Information Disclosure Statement
Per MPEP 609.02(I) and (II)(A)(2), the examiner of a continuing application will consider information which has been considered by the Office in the parent application. Therefore, information considered in parent application 15/031,285 has been considered during examination of the instant application. However, if applicant wants said considered information to be printed on any patent resulting from the instant application, applicant must ensure that said information appears on either an IDS or an 892 in the instant application.
Specification
The abstract of the disclosure is objected to because of the following minor informalities:
In line 2, insert --an-- after “with”.
In line 4, insert --a-- before “first”.
In line 5, replace “includes” with --including--.
In lines 5-6, replace “ALUs (arithmetic logic unit)” with --arithmetic logic units (ALUs)--.
In line 6, insert --a-- before “second”.
In line 7, replace “includes” with --including--.
In lines 5-6, replace “FPUs (floating point unit)” with --floating point units (FPUs)--.
In the last line, replace “the memory” with --a memory--.
A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The disclosure is objected to because of the following informalities:
The changes made to the parent specification are not reflected in the instant specification. Thus, please revisit specification objections and amendments in parent application 15/031,285 to correct the instant specification.
Appropriate correction is required.
Drawings
The drawings are objected to for various reasons set forth in multiple Office actions in parent application 15/031,285. Please make the drawings consistent with those in the parent. Additionally, it appears that the brace 412 in FIG.4 should be extended such that it encompasses all MEM units.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Please ensure any replacement is in only black and white to avoid pixelation and further objection. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 23 is objected to because of the following informalities:
In line 2, insert --an-- after “pass”.
Claim 24 is objected to because of the following informalities:
In line 2, the use of “at least one of” appears to be grammatically incorrect in this context and should be deleted.
Claim 25 is objected to because of the following informalities:
The use of “mutually” in this context appears to be incorrect. The examiner recommends rewording the claim to --…wherein at least two FPUs of the second parallel branch have different operation execution latencies.--.
Claim 28 is objected to because of the following informalities:
In line 3, replace “interthread” with --inter-thread-- to match claim 21.
Claim 26 is objected to due to its dependence on an objected-to claim.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 30-31 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 30 recites the following limitations for which there is a lack of antecedent basis:
In line 4, “the at least one memory access stage”, which could refer to that in claim 30, line 2, or to that in claim 21, 3rd to last paragraph.
Claim 31 is rejected due to its dependency on an indefinite claim.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 21-22, 27-28, and 30-31 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-2, 1, 1, 1, and 1, respectively, of U.S. Patent No. 11,797,310. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-2, 1, 1, 1, and 1 of ‘310 anticipate instant claims 21-22, 27-28, and 30-31, respectively. Of note:
Referring to claim 21, the memory access stage of the memory access segment in the 3rd to last paragraph of instant claim 21 is anticipated by the memory unit in the 3rd to last paragraph of claim 1 of ‘310, where the memory unit is of a memory access segment (see column 13, line 28, to column 14, line 5).
Referring to claim 27, claim 1 of ‘310 has taught the processor architecture arrangement according to claim 21, wherein at least one functional unit is controllable through a number of operation selection fields of instruction words (ALUs, FPUs, etc. are controlled by instructions executed by a processor. Instructions include operation selection fields (opcode, operands, etc.) that control the functional units).
Referring to claim 28, claim 1 of ‘310 has taught the processor architecture arrangement according to claim 21, wherein a number of operands for an ALU or an FPU is determined in an operand select stage of the interleaved interthread pipeline in accordance with a number of operand selection fields given in an instruction word (instructions are executed to control ALUs, FPUs, etc. The fields of an instruction dictate how many operands are operated on by the instruction. For instance, an integer add instruction might be encoded to include two operands (to add together). Thus, the instruction fields would select two operands (in an operand select stage) to supply to an ALU).
Claim 23 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of ‘310 in view of Verma et al. (US 7,814,136).
Referring to claim 23, claim 1 of ‘310 has taught the processor architecture arrangement according to claim 21, but has not taught wherein at least two of the FPUs in the second branch are chained together, wherein an FPU may pass operation result to a subsequent FPU in the chain as an operand. However, Verma has taught such in FIG.6, where one FPU feeds a result to another FPU. This allows for compounding calculations as well as pipelining calculations. As a result, it would have been obvious to one of ordinary skill in the art to modify claim 1 of ‘310 such that at least two of the FPUs in the second branch are chained together, wherein an FPU may pass operation result to a subsequent FPU in the chain as an operand.
Claims 25 and 29 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of ‘310 in view of the examiner’s taking of Official Notice.
Referring to claim 25, claim 1 of ‘310 has taught the processor architecture arrangement according to claim 21, but has not taught wherein at least two FPUs of the second parallel branch are mutually of different complexity in terms of operation execution latency. However, Official Notice is taken that floating-point units with different latencies was well known before applicant’s invention. For instance, a floating-point multiplier and floating-point adder are known components, where multiplication takes more time than addition because multiplication is more complicated. As a result, in order to implement different functions of different complexity, it would have been obvious to one of ordinary skill in the art to modify claim 1 of ‘310 such that at least two FPUs of the second parallel branch are mutually of different complexity in terms of operation execution latency.
Referring to claim 29, claim 1 of ‘310 has taught the processor architecture arrangement according to claim 21, but has not taught wherein at least one FPU is configured to execute at least one floating-point operation selected from the group consisting of: addition, subtraction, multiplication, division, comparison, transformation from integer to floating point, transformation from floating point to integer, square root, logarithm, and exponentiation. However, Official Notice is taken that at least one of these operations was well-known to be performed by an FPU before applicant’s invention. Such would allow simple math to be performed on floating-point data. As a result, it would have been obvious to one of ordinary skill in the art to modify claim 1 of ‘310 such that at least one FPU is configured to execute at least one floating-point operation selected from the group consisting of: addition, subtraction, multiplication, division, comparison, transformation from integer to floating point, transformation from floating point to integer, square root, logarithm, and exponentiation.
Allowable Subject Matter
All claims are allowable over the prior art, but not over ‘310.
Claims 24 and 26 are objected to as being dependent upon a rejected base claim, but would be allowable over ‘310 if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 21, the prior art of record has not taught, either individually or in combination, and together with all other claimed features, the limitations on page 3. Applicant may view rejections in the parent application to determine what limitations of claim 21 are taught by the prior art.
Conclusion
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Forsell, “MTAC - A Multithreaded VLIW Architecture for PRAM Simulation”, which was cited by the examiner and used in rejections in the parent application.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David J. Huisman whose telephone number is 571-272-4168. The examiner can normally be reached on Monday-Friday, 9:00 am-5:30 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta, can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/David J. Huisman/Primary Examiner, Art Unit 2183