Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the application No. 18/470,537 filed on 09/20/2023.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 8 and 18-19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US Pub # 2023/0371235 to Ahn et al. (Ahn).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Regarding independent claim 1, Ahn discloses a semiconductor memory device (Fig. 2) comprising:
a substrate (101) that includes an active pattern (ACT);
a bit line structure (BLS) that crosses the active pattern (ACT);
a storage node (160) contact electrically connected (via conductive pad 130 and ¶0036) to the active pattern (ACT) next to the bit line structure (BLS);
a spacer structure (SS and ¶0024) between a side surface of the bit line structure (BLS) and the storage node contact (160, see Fig. 2), wherein an upper surface of the spacer structure (SS) is at a vertical level lower than an upper surface of the bit line structure (BLS; see Examiner’s Mark-up below) with a lower surface of the substrate providing a base reference plane;
an insulating pattern (180) on the spacer structure (SS); and
a landing pad structure (LP) electrically connected (via 165) to the storage node contact (160) and on the spacer structure (SS) and the bit line structure (BLS),
wherein the landing pad structure (LP) comprises:
a first side surface (see Examiner’s Mark-up below) in contact with the spacer structure (SS);
a second side surface (see Examiner’s Mark-up below) in contact with the bit line structure (BLS); and
a third side surface (see Examiner’s Mark-up below) in contact with the insulating pattern (180).
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Regarding claim 2, Ahn discloses wherein the landing pad structure (LP) has a stepped shape in a cross-sectional view (Fig. 2).
Regarding claim 3, Ahn discloses wherein the spacer structure (SS) includes a first spacer (LS) and a second spacer (US) on an upper surface of the first spacer (LS), wherein the first spacer (LS) is a multilayer spacer (151, 152), and wherein the second spacer (US) is a single-layer spacer.
Regarding claim 4, Ahn discloses wherein the second spacer (US) has a closed shape in a plan view (see Figs. 1A and 1B), and wherein the second spacer (US) has a first height between the first spacer (LS) and the insulating pattern (180) and a second height different from the first height between the first spacer (LS) and the landing pad structure (LP).
Regarding claim 8, Ahn discloses wherein a lower portion of the insulating pattern (180) adjacent to the spacer structure (SS) is vertically aligned with the spacer structure (the most bottom lower portion of 180 is vertically aligned with the top most portion of spacer structure US).
Regarding independent claim 18, Ahn discloses a semiconductor memory device (Fig. 2) comprising:
a substrate (101) that includes an active pattern (ACT), the active pattern including a first source/drain region (105a) and a pair of second source/drain regions (105b) spaced apart from each other with the first source/drain region (105a) therebetween;
a device isolation layer (107) on the substrate (101) and in a trench (107 is in the trench) that defines the active pattern (¶0028);
a word line (WL) extending in a first direction that crosses the active pattern (ACT), wherein the word line (WL) is between the first (105a) and second (105b) source/drain regions;
a gate dielectric layer (120) between the word line (WL) and the active pattern (ACT);
a word line capping pattern (125) on the word line (WL);
an interlayer insulating pattern (135a) on the word line capping pattern (125);
a bit line structure (BLS) electrically connected (via DC and DCB) to the first (105a) source/drain region and extending in a second direction that intersects the first direction, wherein the bit line structure (BLS) crosses the active pattern (ACT) and is on the interlayer insulating pattern (135a);
a spacer structure (LS) on a side surface of the bit line structure (BLS), wherein an upper surface of the spacer structure (SS) is at a lower vertical level than an upper surface of the bit line structure (BLS; see Examiner’s Mark-up above in claim 1) with a lower surface of the substrate providing a base reference plane;
a storage node contact (160) electrically connected to at least one of the second source/drain regions (105b), wherein the storage node contact (160) is spaced apart from the bit line structure (BLS) with the spacer structure (US part of SS) therebetween;
a landing pad structure (LP) electrically connected (via 165) to the storage node contact (160);
an insulating pattern (180) on the spacer structure (US part of SS); and
a data storage pattern (CAP) on the landing pad structure (LP),
wherein the landing pad structure (LP) has a stepped shape in a cross-sectional view (see Fig. 2), and wherein the spacer structure (SS) includes a multilayer spacer (LS) on the interlayer insulating pattern (135a; see Fig. 2, cross-sectional II-II’) and a single-layer spacer (US) on the multilayer spacer (LS; see Fig. 2, see cross-sectional view I-I’).
Regarding claim 19, Ahn discloses wherein the landing pad structure (LP) comprises:
a first side surface (see Examiner’s Mark-up in Fig. 1) in contact with the spacer structure (SS);
a second side surface (see Examiner’s Mark-up in Fig. 1) in contact with the bit line structure (BLS); and
a third side surface (see Examiner’s Mark-up in Fig. 1) in contact with the insulating pattern (180).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 9-11 and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over US Pub # 2023/0371235 to Ahn et al. (Ahn) in view of US Pub # 2024/0251549 to Ko et al. (Ko).
Regarding independent claim 9, Ahn discloses a semiconductor device (Fig. 2) comprising:
a substrate (101) that includes an active pattern (ACT), the active pattern including a first source/drain region (105a) and a pair of second source/drain regions (105b) spaced apart from each other;
a bit line structure (BLS) that is electrically connected to the first source/drain region (105a) and crosses the active pattern (ACT);
a storage node contact (160) electrically connected to the second source/drain region (105b);
a spacer structure (SS) on a side of the bit line structure (BLS), wherein an upper surface of the spacer structure (upper surface of US) is at a lower vertical level than an upper surface of the bit line structure (BLS; see Examiner’s Mark-up from claim 1) with a lower surface of the substrate providing a base reference plane;
a landing pad structure (LP) electrically connected (via 165) to the storage node contact (160); and
an insulating pattern (180) on the spacer structure (SS) and adjacent to the landing pad structure (LP),
wherein the spacer structure (SS) comprises:
a first spacer (LS) between the bit line structure (BLS) and the storage node contact (160); and
a second spacer (US) on an upper surface of the first spacer (LS),
wherein the first spacer is a multilayer spacer (151 and 152), and
wherein the second spacer (US) is a single-layer spacer.
Ahn fails to explicitly disclose a second spacer is between the bit line structure and the landing pad structure.
Ko discloses a second spacer (Fig. 16: 360 ¶0105) is between the bit line structure (350c is substantially analogous to a part of the applicant’s own bit line structure) and the landing pad structure (LP).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have utilize the second spacer of Ahn with the second spacer as taught by Ko in order to cover the air gap AG (¶0105).
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Regarding claim 10, Ahn discloses wherein the landing pad structure (LP) has a stepped shape in a cross-sectional view (see Fig. 2).
Regarding claim 11, Ahn discloses wherein the landing pad structure (LP) comprises:
a first side surface (see Examiner’s Mark-up in Fig. 1) in contact with the spacer structure (SS);
a second side surface (see Examiner’s Mark-up in Fig. 1) in contact with the bit line structure (BLS); and
a third side surface (see Examiner’s Mark-up in Fig. 1) in contact with the insulating pattern (180).
Regarding claim 16, Ahn discloses all of the limitations of claim 9 from which this claim depends.
Ahn fails to explicitly disclose wherein a width of a lower surface of the landing pad is equal to a width of an upper surface of the spacer structure.
However, the width of the lower surface of the landing pad and the spacer structure affect the thickness of the semiconductor device. It is known in the art to use width. It would have been obvious to one of ordinary skill in the art at the time of the invention to vary, through routine experimentation, the result effect variable of the width of the lower surface of the landing pad and the spacer structure in order to optimize the functionality of the device (see MPEP §2144.05). Further, the specification contains no disclosure of either the critical nature of the claimed width or any unexpected results arising therefrom and it has been held that where patentability is said to be based upon a particular chosen dimension or upon another variable recited in a claim, the Applicant must show that the chosen dimension is critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990)
Regarding claim 17, Ahn discloses wherein the first spacer (LS) includes an oxide and a nitride (¶0058), and wherein the second spacer includes an oxide (¶0058).
Claims 13-14 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over US Pub # 2023/0371235 to Ahn et al. (Ahn) in view of US Pub # 2024/0244832 to Lee et al. (Lee).
Regarding claims 13 and 20, Ahn discloses all of the limitations of claim 18 from which this claim depends.
Ahn fails to explicitly disclose wherein the landing pad structure comprises: a barrier pattern adjacent to the storage node contact and a landing pad adjacent to the insulating pattern, and wherein the landing pad has a ‘T’-shaped cross section.
Lee discloses (Fig. 2C) wherein the landing pad structure (LP and LIP) comprises:
a barrier pattern (LIP) adjacent to the storage node contact (BC) and
a landing pad (LP) adjacent to the insulating pattern (BLC and ¶0067), and
wherein the landing pad (LP) has a ‘T’-shaped cross section (Fig. 2C).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have provided the landing pad structure of Ahn with the landing pad structure as taught by Lee in order to improve a misalignment margin, thereby reducing process defects and improving yield (¶0093-0094).
Regarding claim 14, Ahn discloses all of the limitations of claim 13 from which this claim depends.
Ahn fails to explicitly disclose wherein the barrier pattern includes a conductive material different from that of the landing pad.
Lee discloses wherein the barrier pattern (LIP such as silicon oxide ¶0075) includes a conductive material different from that of the landing pad (LP such as tungsten, ¶0074) such that one of ordinary skill in the art would be motivated to seek exemplary material known in the art. Lee teaches it was known in the art to use different material for the barrier pattern and landing pad (¶0074) and it would have been obvious to one of ordinary skill in the art at the time of the invention to have selected different material for the barrier pattern and the landing pad so as to improve the reliability of the semiconductor device (¶0092).
Allowable Subject Matter
Claims 5-7, 12 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 5 recites:
wherein the spacer structure (SS) comprises: a first sub-spacer in contact with the bit line structure; a second sub-spacer on a side surface of the first sub-spacer; and a third sub-spacer in contact with the storage node contact, wherein the second sub-spacer is between the first sub-spacer and the third sub-spacer.
Claim 6 recites:
wherein the landing pad structure comprises: a barrier pattern adjacent to the storage node contact; and a landing pad adjacent to the insulating pattern, wherein the landing pad includes a protruding portion between the barrier pattern and the bit line structure, and wherein the protruding portion is vertically aligned with the spacer structure.
Claim 12 recites:
wherein the first spacer comprises:
a first sub-spacer adjacent to the bit line structure;
a second sub-spacer on a side surface of the first sub-spacer; and
a third sub-spacer adjacent to the storage node contact,
wherein the second sub-spacer is between the first sub-spacer and the third sub-spacer.
Claim 15 recites:
wherein a width of a lower surface of the insulating pattern is equal to a width of an upper surface of the spacer structure.
Each of the above recitations, interpreted in combination with all other limitations of the claim and all limitations of any claims they depend from, is not taught or rendered obvious by the prior art of record and are indicated as allowable subject matter.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pub # 2022/0139921 to Kim et al., US Pub # 2023/0112907 to Kim et al., US Pub # 2021/0296321 to Heo et al.
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/MOHSEN AHMADI/Primary Examiner, Art Unit 2896