Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the application No. 18/470,559 filed on February 24, 2026.
Specification
3. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “.
Election/Restrictions
4. Applicant’s election without traverse of claims 1-4, drawn to device, Group I, in the reply filed on 02/24/2026 is acknowledged.
5. Claims 5-20 are cancelled from further consideration pursuant to 37 CFR 1.142(b) as being drawn to nonelected method claims, Group II, there being no allowable generic or linking claim.
6. In addition, the applicant has inserted new device claims 21-24 and new method claims 25-33.
7. Per the original restriction requirement, the applicant elected the device claims and cancelled the method claims. Based on the original election of the device claims, the new method claims 25-33 have been withdrawn from examining.
Claim Rejections - 35 USC § 102
8. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
9. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
10. Claims 1-4, 21-24 are rejected under 35 U.S.C. 102(a)(1)/ (a)(2) as¶ being anticipated by Huang et al. (US 2021/0296283 A1).
Regarding independent claim 1, Huang et al. teaches an integrated passive device capacitor (Fig. 1) comprising:
a first trench capacitor (126, para [0028] bottom-one) disposed over a substrate (110, para [0028]); and
a second trench capacitor (126, para [0028] top-one) disposed over the first trench capacitor (126 bottom-one), wherein:
a primary electrode (128-1, para [0031] bottom) of the first trench capacitor (126 bottom-one) is electrically connected to a primary electrode (128-1 upper) of the second trench capacitor (126 top-one); and
a secondary electrode (128-2 bottom) of the first trench capacitor (126 bottom-one) is electrically connected to a secondary electrode (128-2 upper) of the second trench capacitor (126 top-one).
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604
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Regarding claim 2, Huang et al. teaches wherein (Fig. 1), the first trench capacitor (126 bottom-one) and the second trench capacitor (126 top-one) are interconnected in a manner effective to increase (by adding/summing) a capacitance density of the integrated passive device capacitor (102) relative to a capacitance density of the first trench capacitor (126 bottom-one) and a capacitance density of the second trench capacitor (126 top-one).
Regarding claim 3, Huang et al. teaches wherein (Fig. 1), the second trench capacitor (126 top-one) is disposed within a layer (114a, para [0035]) of insulating material (silicon oxide, para [0035]) and respective primary electrodes (128), secondary electrodes (128), and dielectric layers (130, para [0031]) of the first (126 bottom-one) and second (126 top-one) trench capacitors are connected through material filled vias (120/122) formed in the layer of insulating material (114a).
Regarding claim 4, Huang et al. teaches wherein (Fig. 1), comprising a multilayer stack of N (4) co-integrated trench capacitors, wherein N>2.
Regarding claim 21, Huang et al. teaches wherein (Fig. 1), the substrate (110) comprises glass or a semiconductor (silicon, para [0026]).
Regarding claim 22, Huang et al. teaches wherein (Fig. 1), the first trench capacitor (126 bottom-one, refer to Fig. 14) is disposed within a trench (1202, para [0076] refer to Fig.12) in a first insulating layer (118a, para [0076]) overlying the substrate (110a).
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Regarding claim 23, Huang et al. teaches wherein (Fig. 1), the second trench capacitor (126 top-one) is disposed within a trench (104, para [0025]) in a second insulating layer (118) overlying the first insulating layer (118a).
Regarding claim 24, Huang et al. teaches wherein (Fig. 1), the first (126 bottom-one) and second (126 top-one) trench capacitors are connected in parallel (para [0028]).
Examiner’s Note
11. Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraphs and/or columns/lines in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
12. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DIDARUL MAZUMDER whose telephone number is (571)272-8823. The examiner can normally be reached M-F 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
13. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DIDARUL A MAZUMDER/Primary Examiner, Art Unit 2812
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