Prosecution Insights
Last updated: October 02, 2026
Application No. 18/470,729

MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

Final Rejection §102
Filed
Sep 20, 2023
Priority
Apr 13, 2023 — RE 10-2023-0048638
Examiner
PATERSON, BRIGITTE A
Art Unit
2896
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
SK hynix Inc.
OA Round
2 (Final)
76%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allowance Rate
297 granted / 388 resolved
+8.5% vs TC avg
Strong +23% interview lift
Without
With
+22.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
21 currently pending
Career history
411
Total Applications
across all art units

Statute-Specific Performance

§101
1.4%
-38.6% vs TC avg
§103
46.6%
+6.6% vs TC avg
§102
27.0%
-13.0% vs TC avg
§112
23.6%
-16.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 388 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-6, 10-16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 20210265383 A1 (Kim). Re claim 1, Kim teaches a memory device comprising: first material layers (insulating layers 22) alternately stacked with second material layers (conductive layers 21); a vertical hole passing through the first material layers and the second material layers (Fig. 3A); first insulating patterns (insulating patterns 23) protruding from a side surface of the first material layers exposed through the vertical hole; a blocking layer (blocking pattern 24) formed along a surface of the second material layers exposed between the first insulating patterns, the blocking layer comprising a plurality of concave sections, each of which is between the first insulating patterns (Fig. 3A); and charge trap patterns (data storage patterns 25) formed in the concave portions, wherein portions of the blocking layer are exposed between the charge trap patterns, wherein a tunnel insulating layer (tunnel insulating layer 26), a channel layer (channel layer 27), and a core pillar (gap-fill layer 28), are formed in an area that is surrounded by the charge trap patterns (Fig. 3A); wherein the blocking layer is disposed continuously in a direction where the first material layers and the second material layers are stacked (direction II Fig. 3A). PNG media_image1.png 594 499 media_image1.png Greyscale Re claim 2, Kim teaches wherein the first material layers are insulating layers, and the second material layers are conductive layers (insulating layers 22 and conductive layers 21). Re claim 3, Kim teaches wherein the blocking layer extends over exposed surfaces of the first insulating patterns and the second material layers, in the vertical hole (Fig. 3A). Re claim 4, Kim teaches wherein the charge trap patterns are radially aligned with the second material layers (Fig. 3A). Re claim 5, Kim teaches wherein the charge trap patterns are spaced apart from each other (Fig. 3A). Re claim 6, Kim teaches wherein a width of the first material layers is the same as a width of the second material layers (Fig. 3A). Re claim 10, Kim teaches wherein the charge trap patterns are spaced apart from the first insulating patterns by the blocking layer (Fig. 3A). Re claim 11, Kim teaches wherein at least one of the first insulating patterns has ring shape (Fig. 3A). Re claim 12, Kim teaches wherein at least one of the charge trap patterns has ring shape (Fig. 3A). Re claim 13, Kim teaches wherein the first insulating patterns are spaced apart from each other by the blocking layer and at least one of the charge trap patterns (Fig. 3A). Re claim 14, Kim teaches wherein the tunnel insulating layer is in contact with the charge trap patterns and the blocking layer (Fig. 3A). Re claim 15, Kim teaches wherein the first insulating patterns protrude towards the tunnel insulating layer more than side surfaces of the second material layers (Fig. 3A). Re claim 16, Kim teaches wherein the second material layers protrude towards the tunnel insulating layer more than inner side surfaces (surfaces abutting layer 12) of the first insulating patterns (Fig. 3A). Response to Arguments Applicant’s arguments with respect to the pending claim(s) have been considered but are moot because the new ground of rejection does not rely on the embodiment of the reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIGITTE A PATERSON whose telephone number is (571)272-1752. The examiner can normally be reached Monday-Friday 9:00AM-5:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at 571-272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. BRIGITTE A. PATERSON Primary Examiner Art Unit 2896 /BRIGITTE A PATERSON/Primary Examiner, Art Unit 2896
Read full office action

Prosecution Timeline

Sep 20, 2023
Application Filed
Mar 23, 2026
Non-Final Rejection mailed — §102
Jun 23, 2026
Response Filed
Sep 22, 2026
Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
76%
Grant Probability
99%
With Interview (+22.6%)
2y 8m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 388 resolved cases by this examiner. Grant probability derived from career allowance rate.

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