Prosecution Insights
Last updated: April 19, 2026
Application No. 18/470,729

MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

Non-Final OA §102§112
Filed
Sep 20, 2023
Examiner
PATERSON, BRIGITTE A
Art Unit
2896
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
SK Hynix Inc.
OA Round
1 (Non-Final)
76%
Grant Probability
Favorable
1-2
OA Rounds
2y 11m
To Grant
99%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allow Rate
283 granted / 371 resolved
+8.3% vs TC avg
Strong +23% interview lift
Without
With
+23.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
31 currently pending
Career history
402
Total Applications
across all art units

Statute-Specific Performance

§101
1.2%
-38.8% vs TC avg
§103
45.1%
+5.1% vs TC avg
§102
30.1%
-9.9% vs TC avg
§112
22.2%
-17.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 371 resolved cases

Office Action

§102 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Claims 7-9 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 1/21/2026. Claim Objections Claim 1 is objected to because of the following informalities: claim 1 recites “wherein portions of the blocking layer exposed between the charge trap patterns”. This limitation is grammatically incorrect. Appropriate correction is required. Suggestion: wherein portions of the blocking layer are exposed between the charge trap patterns Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-6, and 10-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 recites “wherein a tunnel insulating layer, a channel layer, and a core pillar, are formed in an area that is substantially surrounded by the charge trap patterns.” The underlined portion renders the claim indefinite. The term " substantially " is a relative term which renders the claim indefinite; it is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. “Substantially” is defined as " being largely but not wholly that which is specified” (see Merriam Webster online dictionary). This language is indefinite as the specification does not describe how much of the area having the tunnel insulating layer, channel layer and core pillar must be surrounded by the charge trap patterns in order to be considered “substantially surrounded”. The term “substantially” modifies a target, and implicitly requires boundaries at some maximum value above the target and at some minimum value below the target beyond which one is not “substantially” the target any more. Neither the claims, nor the specification, defines these boundaries. Thus, it is unclear whether one must be within some small percentage of deviation of the target (such as 0.01 %, 0.1 %, 1 %, 2 %, 5 %, 10 %, or some other percentage) or within a certain number of units of the target and specifically which of these possible values defines the boundaries. If one were to poll 100 people having ordinary skill in the art, there would be many different responses for the boundaries. Thus, determining whether one is infringing the limitation is subjective, rather than objective, and thus the claim is unclear. Therefore, the claims are rejected as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Claim 6 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 6 recites “wherein a width of the first material layers is substantially the same as a width of the second material layers.” The underlined portion renders the claim indefinite. The term " substantially " is a relative term which renders the claim indefinite; it is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. “Substantially” is defined as " being largely but not wholly that which is specified” (see Merriam Webster online dictionary). This language is indefinite as the specification does not describe how much the width of the first material layers can deviate from the width of the second material layers in order to be considered “substantially the same”. The term “substantially” modifies a target, and implicitly requires boundaries at some maximum value above the target and at some minimum value below the target beyond which one is not “substantially” the target any more. Neither the claims, nor the specification, defines these boundaries. Thus, it is unclear whether one must be within some small percentage of deviation of the target (such as 0.01 %, 0.1 %, 1 %, 2 %, 5 %, 10 %, or some other percentage) or within a certain number of units of the target and specifically which of these possible values defines the boundaries. If one were to poll 100 people having ordinary skill in the art, there would be many different responses for the boundaries. Thus, determining whether one is infringing the limitation is subjective, rather than objective, and thus the claim is unclear. Therefore, the claim is rejected as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-6, 10-16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 20210265383 A1 (Kim). Re claim 1, Kim teaches a memory device comprising: first and second material layers (insulating layers 12 and conductive layers 11) alternately stacked; a vertical hole passing through the first and second material layers (Fig. 2A); first insulating patterns (insulating patterns 13’) protruding from a side surface of the first material layers exposed through the vertical hole; a blocking layer (blocking pattern 14B) formed along a surface of the second material layers exposed between the first insulating patterns, the blocking layer comprising a plurality of concave portions, each of which is between the first insulating patterns (Fig. 2A); and charge trap patterns (data storage patterns 15B) formed in the concave portions, wherein portions of the blocking layer exposed between the charge trap patterns, wherein a tunnel insulating layer (tunnel insulating layer 16), a channel layer (channel layer 17), and a core pillar (gap-fill layer 18), are formed in an area that is substantially surrounded by the charge trap patterns (Fig. 2A). PNG media_image1.png 564 509 media_image1.png Greyscale Re claim 2, Kim teaches wherein the first material layers are insulating layers, and the second material layers are conductive layers (insulating layers 12 and conductive layers 11). Re claim 3, Kim teaches wherein the blocking layer extends over exposed surfaces of the first insulating patterns and the second material layers, in the vertical hole (Fig. 2A). Re claim 4, Kim teaches wherein the charge trap patterns are radially aligned with the second material layers (Fig. 2A). Re claim 5, Kim teaches wherein the charge trap patterns are spaced apart from each other (Fig. 2A). Re claim 6, Kim teaches wherein a width of the first material layers is substantially the same as a width of the second material layers (Fig. 2A). Re claim 10, Kim teaches wherein the charge trap patterns are spaced apart from the first insulating patterns by the blocking layer (Fig. 2A). Re claim 11, Kim teaches wherein at least one of the first insulating patterns has ring shape (Fig. 2A). Re claim 12, Kim teaches wherein at least one of the charge trap patterns has ring shape (Fig. 2A). Re claim 13, Kim teaches wherein the first insulating patterns are spaced apart from each other by the blocking layer and at least one of the charge trap patterns (Fig. 2A). Re claim 14, Kim teaches wherein the tunnel insulating layer is in contact with the charge trap patterns and the blocking layer (Fig. 2A). Re claim 15, Kim teaches wherein the first insulating patterns protrude towards the tunnel insulating layer more than side surfaces of the second material layers (Fig. 2A). Re claim 16, Kim teaches wherein the second material layers protrude towards the tunnel insulating layer more than inner side surfaces (surfaces abutting layer 12) of the first insulating patterns (Fig. 2A). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIGITTE A PATERSON whose telephone number is (571)272-1752. The examiner can normally be reached Monday-Friday 9:00AM-5:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at 571-272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. BRIGITTE A. PATERSON Primary Examiner Art Unit 2896 /BRIGITTE A PATERSON/Primary Examiner, Art Unit 2896
Read full office action

Prosecution Timeline

Sep 20, 2023
Application Filed
Mar 18, 2026
Non-Final Rejection — §102, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12588352
ENERGY LEVELS AND DEVICE STRUCTURES FOR PLASMONIC OLEDS
2y 5m to grant Granted Mar 24, 2026
Patent 12588495
BONDING ALIGNMENT MARKS AT BONDING INTERFACE
2y 5m to grant Granted Mar 24, 2026
Patent 12583740
INTER-POLY CONNECTION FOR PARASITIC CAPACITOR AND DIE SIZE IMPROVEMENT
2y 5m to grant Granted Mar 24, 2026
Patent 12581709
TELLURIUM OXIDE, AND THIN FILM TRANSISTOR COMPRISING SAME AS CHANNEL LAYER
2y 5m to grant Granted Mar 17, 2026
Patent 12568866
SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME
2y 5m to grant Granted Mar 03, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

1-2
Expected OA Rounds
76%
Grant Probability
99%
With Interview (+23.4%)
2y 11m
Median Time to Grant
Low
PTA Risk
Based on 371 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month