DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 recites “A semiconductor device manufacturing method comprising: preparing a first region and a second region on a substrate; forming a tunneling gate insulating layer and a floating gate Poly-Si layer in a first region and a second region of a substrate…”. The claim uses indefinite articles and the same claim terms in the first two clauses for each of “a first region”, “a second region” and “a substrate”. It is unclear if the second instance of each of these terms is referring to the first recitation thereof or whether the claim requires “a first region”, “a second region” and “a substrate” in addition to and/or wholly apart from “a first region”, “a second region” and “a substrate” of the first clause. Therefore, the claims are rejected as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-4, 7-13 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20230262975 A1 (Jia) further in view of US 20180145085 A1 (Liu).
Re claim 1, Jia teaches a semiconductor device manufacturing method comprising:
preparing a first region (MC Area 2) and a second region (HV Area 4 and logic area 6) on a substrate (substrate 10);
forming a tunneling gate insulating layer (oxide layer 12) and a floating gate Poly-Si layer (conductive layer 14 formed of polysilicon [0045]) in a first region and a second region of a substrate;
forming an inter-poly dielectric layer (insulation layer 24) on the floating gate Poly-Si layer;
forming a control gate Poly-Si layer (conductive layer 26 formed of polysilicon [0045]) on the inter-poly dielectric layer;
forming a control gate hard mask layer (hard mask layer 28) on the control gate Poly-Si layer;
performing a patterning process on the control gate hard mask layer, the control gate Poly-Si layer, the inter-poly dielectric layer, the floating gate Poly-Si layer and the tunneling gate insulating layer to form a gate stack comprising a control gate hard mask, a control gate, an inter-poly dielectric pattern, a floating gate and a tunneling gate insulating pattern ([0048-0051] Figs. 7A-10C);
forming a select gate insulating layer (tunnel oxide 44/insulation layer 46) on the gate stack;
forming a select gate (conductive layer 52) disposed on the select gate insulating layer, wherein the select gate is disposed on one sidewall of the gate stack having a spacer shape (Figs. 15A-16C);
performing a removing process on the select gate insulating layer and the control gate hard mask to expose a top surface of the control gate (Figs. 17A-18C).
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Jia does not explicitly teach forming a silicide on the control gate 26. However, Jia does teach forming silicides on the erase gates, select gates and HV logic gates (Figs. 18A-18C).
Liu teaches forming a 2D array of floating gate memory transistors wherein a silicide 176 is formed on the control gate 118 ([0053] Fig. 9A).
It would have been obvious to one of ordinary skill in the art at the time of filing to add the invention of Liu, including forming a silicide on the control gate of Jia.
The motivation to do so is that silicides provide the predictable result of reducing contact resistance at the interface of the gat and overlying conductive metal contact regions ([0054]).
Re claim 2, Jia teaches wherein the performing of a removing process comprises: coating an organic bottom anti-reflective coating (BARC) layer (BARC material 70) on the gate stack; partially removing the BARC layer disposed on the gate stack, resulting in exposing the select gate insulating layer (Figs. 17A-17C [0057]); removing the select gate insulating layer and the control gate hard mask disposed on the control gate; and removing the remaining BARC layer (Figs. 18A-18C [0058]).
Re claim 3, Jia teaches wherein the partially removing of the BARC layer comprises a dry etch-back process (anisotropic etch [0057]).
Re claim 4, Jia teaches wherein the removing of the select gate insulating layer and the control gate hard mask disposed on the control gate comprises at least one of a dry etching process, a wet etching process, or a combination thereof ([0057-0058]).
Re claim 7, Jia teaches wherein the BARC comprises: a first portion covered on the gate stack; and a second portion covered on the select gate, the second portion having a thickness greater than a thickness of the first portion ([0057]).
Re claim 8, Jia teaches further comprising: forming a logic gate insulating layer (insulation layer 24) in the second region of the substrate; forming a logic gate Poly-Si layer (conductive layer 26 formed of polysilicon [0048]) on the logic gate insulating layer; and forming a logic gate hard mask layer on the logic gate Poly-Si layer (hard mask layer 28), wherein the logic gate hard mask layer is simultaneously formed with the control gate hard mask layer (Figs. 7A-7C).
Re claim 9, Jia teaches wherein the removing of the BARC layer is implemented while minimizing damage to the tunneling gate insulating layer below the floating gate Poly-Si layer and the inter-poly dielectric pattern between the floating gate Poly-Si layer and the control gate (Figs. 17A-18C [0057-0058]).
Re claim 10, Jia teaches a semiconductor device manufacturing method comprising:
preparing a first region (MC Area 2) and a second region (HV Area 4 and logic area 6) on a substrate (substrate 10);
forming a gate stack in the first region, the gate stack comprising a control gate hard mask (patterned hard mask layer 28), a control gate (patterned conductive layer 26), an inter-poly dielectric pattern (patterned insulation layer 24), a floating gate (patterned conductive layer 14), and a tunneling gate dielectric pattern (patterned insulating layer 12) (Fig. 10A);
forming a stacked structure in the second region, the stacked structure comprising a logic gate insulating layer (dielectric layer 56), a logic gate Poly-Si layer (conductive layer 58 formed of polysilicon [0055]), and a logic gate hard mask layer (hard mask layer 60) (Figs. 14A-14C);
forming a select gate (patterned conductive layer 52) disposed on one sidewall of the gate stack as a spacer shape in the first region;
removing the logic gate hard mask layer disposed on the logic gate Poly-Si layer, and patterning the stacked structure to form a logic gate in the second region ([0055] Figs. 14A-14C);
removing the control gate hard mask to expose the control gate (Fig. 18A).
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Jia does not explicitly teach forming a silicide on the control gate 26. However, Jia does teach forming silicides on the erase gates, select gates and HV logic gates (Figs. 18A-18C).
Liu teaches forming a 2D array of floating gate memory transistors wherein a silicide 176 is formed on the control gate 118 ([0053] Fig. 9A).
It would have been obvious to one of ordinary skill in the art at the time of filing to add the invention of Liu, including forming a silicide on the control gate of Jia.
The motivation to do so is that silicides provide the predictable result of reducing contact resistance at the interface of the gat and overlying conductive metal contact regions ([0054]).
Re claim 11, Jia teaches wherein the removing of the control gate hard mask comprises: forming a coating layer (BARC layer 70) to cover the gate stack and the stacked structure; partially etching the coating layer to expose the control gate hard mask layer; removing the control gate hard mask layer; and removing the coating layer disposed on the gate stack and the stacked structure ( [0057-0058] Figs. 17A-18A).
Re claim 12, Jia teaches wherein the coating layer comprises a bottom anti-reflective coating (BARC) layer ([0057]).
Re claim 13, Jia teaches wherein the forming of the gate stack in the first region comprises:
forming a tunneling gate insulating layer (oxide layer 12) and a floating gate Poly-Si layer (conductive layer 14 formed of polysilicon [0045]) in a first region and a second region of a substrate;
forming an inter-poly dielectric layer (insulation layer 24) on the floating gate Poly-Si layer;
forming a control gate Poly-Si layer (conductive layer 26 formed of polysilicon [0045]) on the inter-poly dielectric layer;
forming a control gate hard mask layer (hard mask layer 28) on the control gate Poly-Si layer; and
performing a patterning process on the control gate hard mask layer, the control gate Poly-Si layer, the inter-poly dielectric layer, the floating gate Poly-Si layer and the tunneling gate insulating layer to form a gate stack comprising a control gate hard mask, a control gate, an inter-poly dielectric pattern, a floating gate and a tunneling gate insulating pattern ([0048-0051] Figs. 7A-10C).
Re claim 15, Jia teaches wherein the removing of the control gate hard mask layer comprises at least one of a dry etching process, a wet etching process or a combination thereof (anisotropic etch [0057]).
Claim(s) 5-6, 14 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20230262975 A1 (Jia) further in view of US 20180145085 A1 (Liu) further in view of US 20100279510 A1 (Nozawa).
Re claims 5 and 6, Jia and Liu teach the semiconductor device manufacturing method of claim 3, but Jia does not explicitly teach wherein the removing of the remaining BARC layer comprises a plasma ashing process (claim 5) nor wherein the dry etch-back process comprises a descum process, and wherein a process condition in the descum process comprises an oxygen flow rate and a plasma power lower than those of the plasma ashing process (claim 6).
However, Jia teaches that the BARC layer is a photoresist material and that the BARC layer is formed on the top of the gate stacks but etched back and then removed after further processing ([0057-0058]). However, Jia does not provide any substantive detail regarding how the etching and removal is performed.
Nozawa teaches plasma ashing to remove large portions of photoresist material and lower power plasma with lower oxygen flow rate for descumming to remove photoresist residues ([0134-0135]).
It would have been obvious to one of ordinary skill in the art at the time of filing to use the teachings of Nozawa in the BARC removal and patterning in Jia.
The motivation to do so is that since Jia is silent with regards to appropriate etching details of the photoresist material the ordinary skilled artisan would need to look to Nozawa to find appropriate etching parameters to both perform the removal process of Jia and also to perform the desired cleaning of photoresist residue as taught in Nozawa.
Re claims 14 and 16, Jia and Liu teach the semiconductor device manufacturing method of claim 11, wherein the partially etching of the coating layer comprises a descum process using oxygen plasma (claim 12) nor wherein the removing of the coating layer disposed on the gate stack and the stacked structure comprises an ashing process using oxygen plasma, and wherein the descum process operates at oxygen flow rates lower than a plasma ashing process (claim 16).
However, Jia teaches that the BARC layer is a photoresist material and that the BARC layer is formed on the top of the gate stacks but etched back and then removed after further processing ([0057-0058]). However, Jia does not provide any substantive detail regarding how the etching and removal is performed.
Nozawa teaches plasma ashing to remove large portions of photoresist material and lower power plasma with lower oxygen flow rate for descumming to remove photoresist residues ([0134-0135]).
It would have been obvious to one of ordinary skill in the art at the time of filing to use the teachings of Nozawa in the BARC removal and patterning in Jia.
The motivation to do so is that since Jia is silent with regards to appropriate etching details of the photoresist material the ordinary skilled artisan would need to look to Nozawa to find appropriate etching parameters to both perform the removal process of Jia and also to perform the desired cleaning of photoresist residue as taught in Nozawa.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
CN 113380813 A (Lin)
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CN 107210202 A (Yang)
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US 20150054044 A1 (Perera)
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US 20080029805 A1 (Shimamoto)
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US 20050176202 A1 (Hisamoto)
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BRIGITTE A. PATERSON
Primary Examiner
Art Unit 2896
/BRIGITTE A PATERSON/Primary Examiner, Art Unit 2896
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