DETAILED ACTION
This Office action is responsive to Applicant’s response submitted 05 March 2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Patent 8,786,942 to Palese et al.
In regards to claim 1, Palese recites a photonic integrated circuit (Figure 3) comprising: a linewidth reducing circuit (12) comprising an output (output is between element 12 & 50); and an amplifier circuit, connected to the output, comprising: a power splitter (50) comprising a first array of n waveguides distributing power of signal, when received from the output, into a plurality of n split output signals so that the ith one of the split signals is transmitted in the ith one of the waveguides (for 1<i≤ n); and a first plurality of n amplifiers, wherein the ith one of the amplifiers is connected to the ith one of the waveguides to amplify the ith one of the split signals to form an ith amplified signal of a plurality of n amplified signals.
In regards to claim 2, Palese recites the linewidth reducing circuit is coupled to, or comprises, a modulator (Column 3 & 5) modulating an input signal to form the signal.
In regards to claim 3, Palese recites the modulator comprises an IQ coherent modulator, an amplitude modulator, or a phase modulator. (Column 3)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4, 12-15, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent 8,786,942 to Palese et al.
In regards to claims 4 and 20, although Palese does not expressly recite the modulator is programmable to modulate the input signal with a waveform having a phase and/or amplitude for a remote sensing or LIDAR application, encoding data in a communication or computing application, or generating and/or processing an arbitrary complex waveform and configured for generating and/or processing and outputting an arbitrary complex waveform, Palese does teach the modulator to modulate the signal to manipulate amplitude and phase. Furthermore, it is noted that, an apparatus claim must be structurally distinguishable from the prior art. While features of an apparatus may be recited either structurally or functionally, claims directed to an apparatus must be distinguished from the prior art in terms of structure rather than function (In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997); See MPEP 2114 [R-1]). A claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus if the prior art apparatus teaches all the structural limitations of the claim (Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987); see MPEP 2114 [R-1]). Since Palese teaches the modulator to manipulate of amplitude and phase, it would have been obvious before the effective filing date to a person having ordinary skill in the art for the modulator to be capable of performing the function of being programmable to modulate the input signal with a waveform having a phase and/or amplitude for a remote sensing or LIDAR application, encoding data in a communication or computing application, or generating and/or processing an arbitrary complex waveform and configured for generating and/or processing and outputting an arbitrary complex waveform.
In regards to claim 12, although a second array of n waveguides comprising a first side connected to the amplifier circuit and a junction connecting the n waveguides in the second array at a second side, wherein: the ith waveguide in the second array is coupled to the ith one of the amplifiers so that the amplified signals are coherently combined in the junction is not expressly recited, the inclusion of a second array of n waveguides would have be necessary in order to transmit each of the signal from each of the amplifiers in the amplifier array and then combined by a combiner (27). Therefore, although not expressly stated, it would have been obvious before the effective filing date to a person having ordinary skill in the art to have provided although a second array of n waveguides comprising a first side connected to the amplifier circuit and a junction connecting the n waveguides in the second array at a second side, wherein: the ith waveguide in the second array is coupled to the ith one of the amplifiers so that the amplified signals are coherently combined in the junction.
In regards to claims 13 and 14, although Palese does not expressly recite a single chip or a first and second chip, Applicant claims both a single chip and multiple chips. Since Applicant claims both a single and multiple chips and further since it does not appear a particular number of chips solves a stated problem or is for a particular purpose, it would have been obvious before the effective filing date to a person having ordinary skill in the art to have provided a single chip or a first and second chip.
In regards to claim 15, Palese recites a chip comprising indium phosphide comprising the photonic integrated circuit of claim 1 patterned in the indium phosphide.
Allowable Subject Matter
Claim 5-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
In regards to claims 5 and 6, the prior art of record fails to disclose or reasonably suggest an input; a coupler for coupling the signal from the linewidth reducing circuit to a second signal received at the input; a second modulator modulating the second signal, when received from the coupler, to form a modulated second signal; and a plurality of output ports outputting the amplified signals and the modulated second signal off the chip in addition to the accompanying features of the independent claim and any intervening claims.
In regards to claim 7, the prior art of record fails to disclose or reasonably suggest the linewidth reducing circuit comprises: a first coupler having a first coupler input, a first coupler output, and a second coupler output, the first coupler coupling an input signal into a first portion at the first coupler output and a second portion at the second coupler output; a delay line or feedback mechanism delaying the first portion, when received from the first coupler output, with respect to the second portion so as to form a delayed portion; and a mixer mixing the delayed portion with the second portion, when received from the second coupler output, to form an error signal corresponding to a comparison between a frequency of the delayed portion and a frequency of the second portion; and wherein the error signal can used as feedback to control a frequency of a laser outputting the input signal in addition to the accompanying features of the independent claim and any intervening claims.
Claims 16 and 17 are allowed. The prior art of record fails to disclose or reasonably suggest a photonic integrated circuit, comprising: a first coupler having a first coupler input, a first coupler output, and a second coupler output, the first coupler coupling an input signal into a first portion at the first coupler output and a second portion at the second coupler output; a delay line or feedback mechanism coupled to the first coupler and delaying the first portion, when received from the first coupler output, with respect to the second portion so as to form a delayed portion; and a mixer mixing the delayed portion with the second portion, when received from the second coupler output, to form an error signal corresponding to a comparison between a frequency of the delayed portion and a frequency of the second portion; wherein the error signal can be used as feedback to control a frequency of a laser outputting the input signal in addition to the accompanying features of the independent claim and any intervening claims.
Claims 18 and 19 are allowed. The prior art of record fails to disclose or reasonably suggest a photonic integrated circuit, comprising: an input for a coherent receiver signal; a laser; a multimode interference coupler having a first input for receiving the coherent receiver signal; a second output for receiving to a laser signal outputted from the laser; a first output; and a second output; a first modulator connected to the first output modulating the coherent receiver signal, when received, to form a modulated receiver signal; a second modulator connected to the first modulator and the second output for modulating the laser signal when received from the second output; a receiver amplifier connected to the first modulator for amplifying the modulated receiver signal; and an amplifier circuit comprising: a power splitter distributing power of a signal received from second modulator, into a plurality of n split signals so that the ith one of the split signals is transmitted in the ith one of the waveguides (for 1<i≤n); and a plurality of n amplifiers, wherein the ith one of the amplifiers is connected to the ith one of the waveguides to amplify the ith one of the split signals to form an ith amplified signal of a plurality of n amplified signals; and a plurality of output ports for outputting each of the amplified signals in addition to the accompanying features of the independent claim and any intervening claims.
A close prior art of record is U.S. Patent 8,786,942 to Palese. Palese recites a system comprising a photonic circuit system having a series of amplifiers, an array of waveguides and power splitters and further including a feedback loop. However, Palese fails to teach a second modulator configured as claimed by Applicant, where the second modulator receives an input from the first modulator and forms a second modulated signal from the first modulator. Palese further fails to teach a mixer receiving a signal from a feedback mechanism for comparing and providing an error signal to control the frequency of the input signal.
Another prior art of record is U.S. Patent 9,503,196 to Galvanauskas. Galvanauskas discloses a system comprising a photonic circuit system having a series of amplifiers, an array of waveguides and power splitters and further including an array of modulators (Figure 1) but fails to teach the specific configuration of components. More specifically, Galvanauskas fails to teach a second modulator connected to the first modulator and the second output for modulating the laser signal when received from the second output and a mixer mixing the delayed portion with the second portion, when received from the second coupler output, to form an error signal corresponding to a comparison between a frequency of the delayed portion and a frequency of the second portion; wherein the error signal can be used as feedback to control a frequency of a laser outputting the input signal.
Response to Arguments
Applicant’s arguments have been considered but are moot because the new ground of rejection does not rely on any reference as currently applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. In consideration of the arguments, the rejection regarding the output of the linewidth circuit has been modified to reflect an amplifier circuit connected to that output. The output of the linewidth circuit is characterized by the arrow between element 12, the linewidth circuit, and 50, the power splitter.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TINA M WONG whose telephone number is (571)272-2352. The examiner can normally be reached M-F 8:30-5:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Uyen-Chau Le can be reached at (571) 272-2397. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TINA WONG/Primary Examiner, Art Unit 2874