Prosecution Insights
Last updated: October 25, 2026
Application No. 18/471,003

Corrosion Resistant Metal Structures for Wide Bandgap Semiconductor Devices

Non-Final OA §103
Filed
Sep 20, 2023
Examiner
HAN, JONATHAN
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Wolfspeed Inc.
OA Round
3 (Non-Final)
84%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allowance Rate
1085 granted / 1294 resolved
+15.8% vs TC avg
Moderate +10% lift
Without
With
+9.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
25 currently pending
Career history
1324
Total Applications
across all art units

Statute-Specific Performance

§101
1.3%
-38.7% vs TC avg
§103
55.4%
+15.4% vs TC avg
§102
32.1%
-7.9% vs TC avg
§112
9.3%
-30.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1294 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 09/21/2026 has been entered. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 1, 6-9, 12, 15, 19, 24-26, 50 and 70 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mieczkowski et al. (U.S. Publication No. 2011/0227089 A1; hereinafter Mieczkowski) in view of Yanagida et al. (U.S. Publication No. 2023/0290888 A1; hereinafter Yanagida) With respect to claim 1, Mieczkowski discloses a semiconductor device, comprising: a wide bandgap semiconductor structure [212]; a metal structure on the wide bandgap semiconductor structure; and wherein the metal structure comprises a metal layer [160] contacting the wide bandgap semiconductor structure wherein the metal structure further comprises at least one of a diffusion barrier layer [180], an adhesion layer [810], or a conductive layer [170] on the metal layer [160] (see Figure 2 and ¶[0034]; diffusion barrier layer, adhesion layer and conductive layers are all present), Mieczkowski fails to disclose the metal layer comprising ruthenium or the metal structure does not include nickel (see ¶[0032]; Mieczkowski utilizes Iridium). In the same field of endeavor, Yanagida teaches utilizing ruthenium as an alternative to Iridium and Nickel (See ¶[0070]). Implementation of ruthenium as taught by Yanagida provides the proper conductivity of the electrode layer. Yanagida also discloses the metal layer being one metal, thereby excluding nickel and not requiring the utilization of nickel as ruthenium provides the necessary conductivity on its own (See ¶[0070]). There is no requirement found within Yanagida that nickel must be included, therefore the metal structure does not include nickel. Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention. With respect to claim 6, the combination of Mieczkowski and Yanagida discloses wherein the metal structure is a Schottky contact with the wide bandgap semiconductor structure (see Mieczkowski Figure 2). With respect to claim 7, the combination of Mieczkowski and Yanagida discloses wherein the metal structure is a gate contact on the wide bandgap semiconductor structure (See Mieczkowski Figure 2). With respect to claim 8, the combination of Mieczkowski and Yanagida discloses wherein a thickness of the metal layer is in a range of about 50 Angstroms to about 200 Angstroms (see Yanagida ¶[0070]). With respect to claim 9, the combination of Mieczkowski and Yanagida discloses wherein the adhesion layer comprises platinum, wherein a thickness of the adhesion layer is about 50 Angstroms to about 300 Angstroms (See Yanagida ¶[0070] and ¶[0073] and Mieczkowski ¶[0034]; other metals with good adhesion characteristics, Platinum is utilized throughout the diffusion/adhesion layers). With respect to claim 12, the combination of Mieczkowski and Yanagida wherein the diffusion barrier layer comprises titanium, wherein a thickness of the diffusion barrier layer is about 100 Angstroms to about 300 Angstroms (See Yanagida ¶[0073] and Mieczkowski ¶[0034]). With respect to claim 15, the combination of Mieczkowski and Yanagida discloses wherein the conductive layer comprises gold, wherein a thickness of the conductive layer is about 1000 Angstroms to about 6000 Angstroms (See Yanagida ¶[0073] and Mieczkowski ¶[0026]). With respect to claim 19, the combination of Mieczkowski and Yanagida discloses wherein the wide bandgap semiconductor structure comprises a Group III-nitride (See Mieczkowski ¶[0023]). With respect to claim 24, the combination of Mieczkowski and Yanagida discloses wherein the semiconductor device is a high electron mobility transistor (See Mieczkowski Figure 2 and ¶[0022]). With respect to claim 25, the combination of Mieczkowski and Yanagida discloses wherein the semiconductor device is a Schottky diode (see Yanagida ¶[0104]). With respect to claim 26, the combination of Mieczkowski and Yanagida discloses wherein the semiconductor device is a MOSFET (see Yanagida ¶[0079]). With respect to claim 50, Mieczkowski discloses a method of forming a semiconductor device, comprising: forming a wide bandgap semiconductor structure [212] on a substrate [320]; forming a gate contact [150] on the wide bandgap semiconductor structure; and wherein the gate contact comprises a metal layer [160], contacting the wide bandgap semiconductor structure; and wherein a metal structure on the wide bandgap semiconductor structure further comprises at least one of a diffusion barrier layer [180], an adhesion layer [810], or a conductive layer [170] on the metal layer [160] (see Figure 2 and ¶[0034]; diffusion barrier layer, adhesion layer and conductive layers are all present). Mieczkowski fails to disclose the metal layer comprising ruthenium or the metal structure does not include nickel (see ¶[0032]; Mieczkowski utilizes Iridium). In the same field of endeavor, Yanagida teaches utilizing ruthenium as an alternative to Iridium and Nickel (See ¶[0070]). Implementation of ruthenium as taught by Yanagida provides the proper conductivity of the electrode layer. Yanagida also discloses the metal layer being one metal, thereby excluding nickel and not requiring the utilization of nickel as ruthenium provides the necessary conductivity on its own (See ¶[0070]). There is no requirement found within Yanagida that nickel must be included, therefore the metal structure does not include nickel. Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention. With respect to claim 70, the combination of Mieczkowski and Yanagida discloses wherein the wide bandgap semiconductor structure is a Group III- Nitride wide bandgap semiconductor structure (See ¶[0023]). Claim(s) 21 and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mieczkowski and Yanagida as applied to claim 19 above, and further in view of Tu et al. (U.S. Publication No. 2023/0352574 A1). With respect to claim 21, the combination of Mieczkowski and Yanagida fails to disclose wherein the wide bandgap semiconductor structure further comprises a barrier layer, a channel layer, and a two-dimensional electron gas (2DEG) at an interface between the channel layer and the barrier layer but does disclose a channel structure with a 2DEG between the source and drain regions (See ¶[0003]). In the same field of endeavor, Tu teaches wherein the wide bandgap semiconductor structure further comprises a barrier layer [120], a channel layer [110], and a two-dimensional electron gas (2DEG) [115] at an interface between the channel layer and the barrier layer (see Figure 1A) Both Tu and Mieczkowski are HEMT structures. Integration of Tu’s specific orientation of the barrier layer, channel and 2DEG allows for more control of the depletion region for specific applications (see Tu ¶[0057]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention With respect to claim 23, the combination of Mieczkowski, Yanagida and Tu discloses wherein the wide bandgap semiconductor structure is on a substrate [230], the substrate comprising silicon carbide (see Mieczkowski ¶[0023]). Claim(s) 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tu in view of Yanagida With respect to claim 27, Tu discloses a transistor device, comprising: a substrate [101]; a Group III-nitride semiconductor structure on the substrate, the Group III-nitride semiconductor structure comprising a barrier layer [120] and a channel layer [110], the barrier layer having a different bandgap relative to the channel layer (see ¶[0050]); a gate contact [150], source contact [130], and a drain contact [140], wherein the gate contact is between the source contact and the drain contact; and wherein the gate contact comprises a plurality of gate stack layers [150/170], wherein at least one of the gate stack layers is a metal layer (See ¶[0051]; Iridium). Tu fails to disclose wherein the metal layer comprises ruthenium or a metal structure on the Group III-nitride semiconductor structure further comprises at least one of a titanium layer, a platinum layer, a gold layer, a copper layer, and a silver layer on the metal layer, and the metal structure does not include nickel In the same field of endeavor, Yanagida teaches the metal layer comprises ruthenium (see ¶[0070]) and a metal structure on the Group III-nitride semiconductor structure further comprises at least one of a titanium layer, a platinum layer, a gold layer, a copper layer, and a silver layer on the metal layer, and the metal structure does not include nickel (See ¶[0077]). Implementation of ruthenium as taught by Yanagida provides the proper conductivity of the electrode layer. Yanagida also discloses the metal layer being one metal, thereby excluding nickel and not requiring the utilization of nickel as ruthenium provides the necessary conductivity on its own (See Yanagida ¶[0070]). There is no requirement found within Yanagida that nickel must be included, therefore the metal structure can be produced to not include nickel. Multiple layered metal layers and structures can be produced to further provide proper conductivity (See Yanagida ¶[0077]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention. Response to Arguments Applicant's arguments filed 09/21/2026 have been fully considered but they are not persuasive. Regarding claims 1, 27 and 50, Applicant argues that “Mieczkowski explicitly teaches a Schottky barrier metal layer that "comprises nickel (Ni), platinum (Pt) and/or iridium (Ir)." Neither Yanagida, Mieczkowski, nor Tu disclose or suggest a metal structure that requires "ruthenium" while explicitly mandating that "the metal structure does not include nickel," as is now recited in the independent claims.” Examiner respectfully disagrees. An express ban on nickel by the prior art is not required to meet the limitations of the claim. Mieczkowski provides a list of acceptable metals utilized with the metal layer, including nickel and iridium. Within the same field of endeavor, Yanagida discloses alternatively utilizing ruthenium as a functional alternative to iridium and nickel. While nickel is still acknowledged as an option, Yanagida explicitly discloses the utilization of a single metal and includes ruthenium within the list of functional metals acceptable for the metal layer. While Yanagida does not expressly forbid the utilization of nickel, it does not explicitly require that the electrode to include nickel as well. As the metal layer of Yanagida can be a single metal and chosen within a list including ruthenium, one of ordinary skill in the art could appreciate that nickel can be excluded based on the preference of one of ordinary skill in the art and substituted with ruthenium, thereby meeting the limitations of the claim of utilizing ruthenium while excluding nickel. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONATHAN HAN whose telephone number is (571)270-7546. The examiner can normally be reached 9.00-5.00PM PST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, STEVEN LOKE can be reached at 571-272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JONATHAN HAN/Primary Examiner, Art Unit 2818
Read full office action

Prosecution Timeline

Show 1 earlier event
Dec 01, 2025
Non-Final Rejection mailed — §103
Feb 10, 2026
Applicant Interview (Telephonic)
Feb 10, 2026
Examiner Interview Summary
Feb 19, 2026
Response Filed
May 19, 2026
Final Rejection mailed — §103
Sep 21, 2026
Request for Continued Examination
Sep 23, 2026
Response after Non-Final Action
Sep 28, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
84%
Grant Probability
93%
With Interview (+9.6%)
2y 4m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 1294 resolved cases by this examiner. Grant probability derived from career allowance rate.

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