DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8, 13-15, 18, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Im et al (US Publication No. 2018/0315740) in view of Mallik et al (US Publication No. 2020/0395313).
Regarding claim 1, Im discloses a package comprising: a first substrate Fig 6A, 201;a first integrated device Fig 6A, 210 comprising a first front side and a first back side, wherein the first front side of the first integrated device is coupled to the first substrate through at least a first plurality of solder interconnects Fig 6A, 213;a second substrate Fig 6A, 300 coupled to the first substrate through at least a second plurality of solder interconnects Fig 6A, 310, wherein the second substrate includes a cavity Fig 6A;a second integrated device Fig 6A, 110 comprising a second front side and a second back side Fig 6A,and wherein the second integrated device is located at least partially in the cavity of the second substrate Fig 6A;and an encapsulation layer Fig 6A, 220 located at least between the first substrate Fig 6A, 201 and the second substrate Fig 6A, 300, wherein the encapsulation layer is coupled to the first substrate, the second substrate and the first integrated device Fig 6A.Im discloses all the limitations but silent on the connection between the first and second integrated device. Whereas
Mallik discloses package Fig 6 comprising: a first substrate Fig 6, 673; a first integrated device Fig 6, 640 ¶0036 coupled to the first substrate Fig 6, 673 through at least a first plurality of solder interconnects Fig 6, 637; a second substrate Fig 6, 630 ¶0035 coupled to the first substrate Fig 6, 673 through at least a second plurality of solder interconnects Fig 6, 637, wherein the second substrate Fig 6, 630 includes a cavity Fig 6; a second integrated device Fig 6, 620 comprising a second front side and a second back side Fig 6,wherein the second front side of the second integrated device is coupled to the first back side of the first integrated device Fig 6, 640 through a third plurality of solder interconnects Fig 6, and an encapsulation layer Fig 6, 674/531/532 located at least between the first substrate Fig 6, 673 and the second substrate Fig 6, 630, wherein the encapsulation layer is coupled to the first substrate, the second substrate and the first integrated device Fig 6. Im and Mallik are analogous art because they are directed to semiconductor package and one of ordinary skill in the art would have had a reasonable expectation of success to modify Im because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the package of Im and incorporate the teachings of Mallik to improve device connectivity and packaging.
Regarding claim 2, Mallik discloses wherein the encapsulation layer Fig 6, 674/531/532 is located in at least part of the cavity of the second substrate Fig 6.
Regarding claim 3, Mallik discloses wherein the encapsulation layer Fig 6, 674/531/532 encapsulates at least part of the first integrated device Fig 6.
Regarding claim 4, Mallik discloses wherein the second substrate includes a solder resist layer ¶0053, and wherein part of the encapsulation layer is located over the solder resist layer Fig 5A-5B.
Regarding claim 5, Mallik discloses wherein the third plurality of solder interconnects touch the first back side of the first integrated circuit Fig 6.
Regarding claim 6, Mallik discloses wherein the second front side of the second integrated device faces towards the first back side of the first integrated device Fig 6 and Fig 5J.
Regarding claim 7, Mallik discloses wherein the encapsulation layer encapsulates at least part of the first integrated device and at least part of the second integrated device Fig 6 and Fig 5J.
Regarding claim 8, Mallik discloses wherein the first integrated device is located at least partially in the cavity of the second substrate Fig 6.
Regarding claim 13, Mallik discloses a third integrated device coupled to the second substrate through a fourth plurality of solder interconnects Fig 6 and Fig 5J.
Regarding claim 14, Im discloses a package comprising: a first substrate Fig 6A, 201;a first integrated device Fig 6A, 210 comprising a first front side and a first back side, wherein the first front side of the first integrated device is coupled to the first substrate through at least a first plurality of solder interconnects Fig 6A, 213;a second substrate Fig 6A, 300 coupled to the first substrate through at least a second plurality of solder interconnects Fig 6A, 310, wherein the second substrate includes a cavity Fig 6A;a second integrated device Fig 6A, 110 comprising a second front side and a second back side Fig 6A,wherein the second front side of the second integrated device faces in a direction towards the first back side of the first integrated device Fig 6A, and wherein there is no electrical path through the first back side of the first integrated device between the first integrated device and the second integrated device Fig 6A; and an encapsulation layer Fig 6A, 220 located at least between the first substrate Fig 6A, 201 and the second substrate Fig 6A, 300, wherein the encapsulation layer is coupled to the first substrate, the second substrate and the first integrated device Fig 6A. Im discloses all the limitations but silent on the connection between the second integrated device and the second substrate. Whereas Mallik discloses package Fig 6 comprising: a first substrate Fig 6, 673; a first integrated device Fig 6, 640 ¶0036 coupled to the first substrate Fig 6, 673 through at least a first plurality of solder interconnects Fig 6, 637; a second substrate Fig 6, 630 ¶0035 coupled to the first substrate Fig 6, 673 through at least a second plurality of solder interconnects Fig 6, 637, wherein the second substrate Fig 6, 630 includes a cavity Fig 6; a second integrated device Fig 6, 620 comprising a second front side and a second back side Fig 6,wherein the second integrated device is coupled to the second substrate through a third plurality of solder interconnects Fig 6, and an encapsulation layer Fig 6, 674/531/532 located at least between the first substrate Fig 6, 673 and the second substrate Fig 6, 630, wherein the encapsulation layer is coupled to the first substrate, the second substrate and the first integrated device Fig 6. Im and Mallik are analogous art because they are directed to semiconductor package and one of ordinary skill in the art would have had a reasonable expectation of success to modify Im because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the package of Im and incorporate the teachings of Mallik to improve device connectivity and packaging.
Regarding claim 15, Mallik discloses wherein the second substrate includes an interposer comprising a plurality of interposer interconnects ¶0035.
Regarding claim 18, Mallik discloses a die substrate from the first integrated device includes a plurality of through substrate vias Fig 6.
Regarding claim 20, Mallik discloses wherein the package is implemented in a device that is selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, and a device in an automotive vehicle¶0072-0075.
Claims 9-12 are rejected under 35 U.S.C. 103 as being unpatentable over Im et al (US Publication No. 2018/0315740) and Mallik et al (US Publication No. 2020/0395313) in further view of Refai-Ahmed et al (US Publication No. 2012/0075807).
Regarding claim 9, Im discloses all the limitations but silent on the heat sink. Whereas Refai-Ahmed discloses a thermal interface material Fig 9, 200 coupled to the second integrated device Fig 9; and a heat sink Fig 9, 75 coupled to the second back side of the second integrated device through the thermal interface material Fig 9, 200. Im and Refai-Ahmed are analogous art because they are directed to semiconductor package and one of ordinary skill in the art would have had a reasonable expectation of success to modify Im because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the package of Im and incorporate the teachings of Refai-Ahmed to improve device thermal management.
Regarding claim 10,Mallik discloses the first integrated device and/or the heat sink are located at least partially in the cavity of the second substrate Fig 6.
Regarding claim 11, Refai -Ahmed discloses wherein the heat sink is coupled to the second back side of the second integrated device through the thermal interface material Fig 9.
Regarding claim 12, Refai -Ahmed discloses a third integrated device coupled to the second substrate through a fourth plurality of solder interconnects Fig 7- 9.
Claims 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Im et al (US Publication No. 2018/0315740) in view of Mallik et al (US Publication No. 2020/0395313) and in further view of Karhade et al (US Publication No. 2018/0182744).
Regarding claims 16 and 17, Im discloses all the limitations except for the device thicknesses. Whereas Karhade discloses wherein the first integrated device comprises a die substrate, wherein the die substrate includes a thickness in a range of about 32–792 micrometers ¶0039-0040, and wherein the first integrated device includes a thickness in a range of about 40–800 micrometers¶0039-0040 or
wherein the first substrate includes a thickness in a range of about 100–300 micrometers¶0039-0040, and wherein the second substrate includes a thickness in a range of about 50–150 micrometers¶0039-0040, and wherein the encapsulation layer includes a thickness in a range of about 100–300 micrometers¶0039-0040. Im and Karhade are analogous art because they are directed to semiconductor package and one of ordinary skill in the art would have had a reasonable expectation of success to modify Im because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the package of Im and incorporate the teachings of Karhade since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (1955).
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Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Im et al (US Publication No. 2018/0315740) in view of Mallik et al (US Publication No. 2020/0395313) and in further view of Lin et al (US Publication No. 2019/0067157).
Regarding claim 19, Im discloses all the limitations but silent on the dummy through vias. Whereas Lin discloses wherein a die substrate from the first integrated device includes a plurality of dummy through substrate vias ¶0017,0024-0025, 0044. Im and Lin are analogous art because they are directed to semiconductor package and one of ordinary skill in the art would have had a reasonable expectation of success to modify Im because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the package of Im and incorporate the teachings of Lin to improve device connectivity and performance.
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CHRISTINE A ENAD/ Primary Examiner, Art Unit 2811
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