Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Status of the Claims
Applicant’s election, without traverse, of claims 1-15 in the reply filed on December 01st, 2025 is acknowledged. Non-elected invention and species, claims 16-28 have been withdrawn from consideration. Claims 1-28 are pending.
Action on merits of Species 1, claims 1-15 as follows.
Priority
Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on September 20th, 2023 has been considered by the examiner.
Drawings
The drawings filed on 09/20/2023 and 12/01/2025 are acceptable.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1-4 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2007/0241407, hereinafter as Kim ‘407) in view of Bedell (US 2015/0287740, hereinafter as Bede ‘740).
Regarding Claim 1, Kim ‘407 teaches a memory device, comprising:
a well (Fig. 4A, (54); [0045]) formed in a substrate (Fig. 4A, (50); [0045];
first (62; [0045]), second (64; [0045]), and third (66; [0047]) junction regions included in the well, the first, second, and third junction regions being spaced apart from each other;
a gate pattern (58; [0045]) disposed on the well between the first (62) and second junction (64) regions; and
a blocking layer (56; [0045]) included in the well, the blocking layer (56) disposed between the second (64) and third (66) junction regions.
Thus, Kim ‘407 is shown to teach all the features of the claim with the exception of explicitly the limitations: “an insulating liner layer formed between the well and the substrate, the insulating liner layer enclosing the well; and the insulating liner layer enclosing the well”.
Bede ‘740 teaches an insulating liner layer (Fig. 2, (55); [0039]) formed between the well (65A; [0039]) and the substrate (60; [0034), the insulating liner layer (55) enclosing the well (65A)
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Kim ‘407 by having an insulating liner layer formed between the well and the substrate, the insulating liner layer enclosing the well; and the insulating liner layer enclosing the well for the purpose of improving performance of the MOSFET device (see para. [0004]) as suggested by Bede ‘740.
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Fig. 4A (Kim ‘407)
Regarding Claim 2, Bede ‘740 teaches the well (65a) is formed of a polysilicon layer including N-type impurities (see para. [0086]).
Regarding Claim 3, Kim ‘407 teaches upper surfaces of the substrate and the well extend in a common plane (see Fig. 4A, para. [0045]).
Regarding Claim 4, Bede ‘740 teaches the insulating liner layer (55; [0039]) is formed of at least one of an oxide layer and a nitride layer.
Regarding Claim 5, Kim ‘407 teaches the first and second junction regions are regions in which P-type impurities are implanted into the well (see para. [0062]).
Product by process limitation:
The expression “are implanted” is/are taken to be a product by process limitation and is given no patentable weight. A product by process claim directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See In re Fessman, 180 USPQ 324, 326 (CCPA 1974); In re Marosi et al., 218 USPQ 289, 292 (Fed. Cir. 1983); In re Brown, 459 F.2d 531, 535, 173 USPQ 685, 688 (CCPA 1972); In re Pilkington, 411 F.2d 1345, 1348, 162 USPQ 145, 147 (CCPA 1969); Buono v. Yankee Maid Dress Corp., 77 F.2d 274, 279, 26 USPQ 57, 61 (2d. Cir. 1935); and particularly In re Thorpe, 227 USPQ 964, 966 (Fed. Cir. 1985), all of which make it clear that it is the patentability of the final structure of the product “gleaned” from the process steps, which must be determined in a “product by process” claim, and not the patentability of the process. See also MPEP 2113. Moreover, an old and obvious product produced by a new method is not a patentable product, whether claimed in “product by process” claims or not.
Regarding Claim 6, Kim ‘407 teaches the third junction region is a region in which N-type impurities are implanted into the well (see para. [0062]).
Product by process limitation:
The expression “are implanted” is/are taken to be a product by process limitation and is given no patentable weight. A product by process claim directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See In re Fessman, 180 USPQ 324, 326 (CCPA 1974); In re Marosi et al., 218 USPQ 289, 292 (Fed. Cir. 1983); In re Brown, 459 F.2d 531, 535, 173 USPQ 685, 688 (CCPA 1972); In re Pilkington, 411 F.2d 1345, 1348, 55 162 USPQ 145, 147 (CCPA 1969); Buono v. Yankee Maid Dress Corp., 77 F.2d 274, 279, 26 USPQ 57, 61 (2d. Cir. 1935); and particularly In re Thorpe, 227 USPQ 964, 966 (Fed. Cir. 1985), all of which make it clear that it is the patentability of the final structure of the product “gleaned” from the process steps, which must be determined in a “product by process” claim, and not the patentability of the process. See also MPEP 2113. Moreover, an old and obvious product produced by a new method is not a patentable product, whether claimed in “product by process” claims or not.
Regarding Claim 7, Kim ‘407 teaches a concentration of the N-type impurities implanted into the third junction region is higher than a concentration of N-type impurities included in the well (see para. [0047] and [0062]).
Regarding Claim 8, Kim ‘407 teaches a gate insulating layer (111; [0063]) disposed on the well (106; [0062]); and a gate conductive layer (112; [0063]) disposed on the gate insulating layer (111) (see Fig. 7).
Regarding Claim 9, Bede ‘740 teaches the gate insulating layer (see para. [0048]) is formed of an oxide layer.
Regarding Claim 10, Bede ‘740 teaches gate conductive layer is formed of at least one of tungsten, molybdenum, cobalt, nickel, silicon, and polysilicon (see para. (0031] and [0048]-[0049]).
Regarding Claim 11, Kim ‘407 teaches portions of the first (62) and second 964) junction regions overlap a portion of the gate pattern (see Fig. 4A).
Regarding Claim 12, Kim ‘407 teaches the blocking layer (56).
Thus, Kim ‘407 and Bede ‘740 are shown to teach all the features of the claim with the exception of explicitly the limitations: “the blocking layer is formed of an oxide layer”.
However, it has been held to be within the general skill of a worker in the art to select an oxide material for the blocking layer material on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. (see para. [0070]) of Kojima (US 2003/0164521) as evidence. A person of ordinary skills in the art is motivated to select an oxide material for the blocking layer material when this improving the performance of the semiconductor device.
Regarding Claim 13, Bede ‘740 teaches a lower surface of the blocking layer (30) is spaced apart from the insulating liner layer (55). Examiner considers the dielectric layer (30) is the blocking layer.
Regarding Claim 14, Kim ‘407 teaches the first (62), second (64), and third (66) junction regions have depths less than that of the blocking layer (56) (see Fig. 4A).
Regarding Claim 15, Kim ‘407 teaches a connection line disposed on the second (64) and third (66) junction regions and configured to electrically connect the second and third junction regions to each other (see Fig. 4A; [0055]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following patents are cited to further show the state of the art with respect to semiconductor devices:
Blanc et al. (US 2008/0224220 A1)
Masuoka et al. (US 2003/0205765 A1)
Yu et al. (US 2003/0207530 A1)
Morishita (US 2001/0006243 A1)
For applicant’s benefit portions of the cited reference(s) have been cited to aid in the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DZUNG T TRAN whose telephone number is (571) 270-3911. The examiner can normally be reached on M-F 8 AM-5PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DZUNG TRAN/
Primary Examiner, Art Unit 2893