DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This OA is in response to the amendments filled on 3/19/2026 that has been entered, wherein claims 1-15 and 18-22 are pending and claims 16-17 are canceled.
Drawings
The objection to the Figs. 1A-1D is withdrawn in light of Applicant’s amendment of 3/19/2026.
Claim Objections
The objection to claim 11 is withdrawn light of Applicant’s amendment of 3/19/2026.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 12-15 and 18-22 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 12 recites the limitation "the gate dielectric layer" in lines 12 and 17. There is insufficient antecedent basis for this limitation in the claim. Is the gate dielectric layer of lines 12 and 17 the same or different than a gate dielectric of line 10? For the purpose of examination “the gate dielectric layer” in lines 12 and 17 will be interpreted as “the gate dielectric”.
Claim 12 recites the limitation "the second portion of the gate dielectric layer" in line 17. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination “the second portion of the gate dielectric layer” in lines 17 will be interpreted as “a second portion of the gate dielectric layer”.
Claims 13-15 and 18-22 depend on claim 12 and inherit its deficiencies.
The term “entirely aligned” in claim 19, line 2 is a relative term which renders the claim indefinite. The term “entirely aligned” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. It is unclear if entirely aligned requires complete overlap in projection along the second direction or matching boundaries of the second portion of the gate dielectric layer and the first of the plurality of source regions or alignment of a side of the of the second portion of the gate dielectric layer and a side of the first of the plurality of source regions or some other geometric relationship? For the purpose of examination, the limitation of “the second portion of the gate dielectric layer is entirely aligned with the first of the plurality of source regions along the second direction” will be interpreted as “ a side of the second portion of the gate dielectric layer is aligned with a side of the first of the plurality of source regions along the second direction”.
Claim 20 recites the limitation of “the second opening has a second depth into the semiconductor layer” in line 2. Since the second opening is define in claim 12, line 13 as a opening in the gate electrode it is unclear how the second opening can have a has a second depth into the semiconductor layer? What is relationship between the second opening and the first openings of claim 12, line 6? Does the second opening overlap or include the plurality of first openings? For the purpose of examination, “the second opening has a second depth into the semiconductor layer” will be interpreted as “the plurality of first openings has a second depth into the semiconductor layer”.
Claim 22 recites the limitation of “the body region is partially aligned with the gate conductive terminal along the second direction” in line 1. It is unclear what “partially aligned” means? Are only some boundaries of the body region and the gate conductive terminal aligned? Do the body region and the gate conductive terminal partially overlap? For the purpose of examination the limitation of “the body region is partially overlapped with the gate conductive terminal along the second direction”
The objection of claims 1-5 and 11-17 is withdrawn in light of Applicant’s amendment of 3/19/2026.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7, 10, 12, 18 and 20-22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kono et al. (US 2017/0271467 A1) of record.
Regarding claim 1, Kono teaches an electronic device(Fig. 1), comprising:
a semiconductor body(10, ¶0020) having a surface(P1, ¶0021);
a body region(28, ¶0025) in the semiconductor body(10, ¶0020), extending along a first direction parallel to the surface(P1, ¶0021) of the semiconductor body(10, ¶0020); and
a source region(30, ¶0031) in the body region(28, ¶0025), extending along the first direction,
a gate dielectric(16a, ¶0018) on the surface of the semiconductor body(10, ¶0020);
a gate terminal(18a, ¶0018) on the gate dielectric(16a, ¶0018);
an L-shaped gate dielectric(20a, ¶0018, please see examiner annotated Fig. 1) directly on both the gate dielectric(16a, ¶0018) and the gate terminal(18a, ¶0018);
a plurality of trenches(22a, 22b, ¶0018) through the source region(30, ¶0031) and extending into the body region(28, ¶0025);
a plurality of raised regions(CP1, ¶0031) alternating with each trench of the plurality of trenches(22a, 22b, ¶0018), each raised region(CP1, ¶0031) being on the source region(30, ¶0031);
a first electrical contact region(CP2,CP3, ¶0037, ¶0042) in each trench(22a, 22b, ¶0018);
a second electrical contact region(CP1, ¶0033) on each raised region(CP1, ¶0031); and
an electrical connection layer(12a, ¶0018) extending with electrical continuity longitudinally to the body and source regions(28, 30, ¶0025, ¶0031), in electrical connection with the first and second electrical contact regions(CP1, CP2, ¶0033, ¶0037) in the plurality of trenches(22a, 22b, ¶0018) and on the plurality of raised regions(CP1, ¶0031).
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Regarding claim 2, Kono teaches the electronic device according to claim 1, wherein the first and second electrical contact regions(CP1, CP2, ¶0033, ¶0037) are contiguous to each other along the first direction(Fig. 3).
Regarding claim 3, Kono teaches the electronic device according to claim 1, wherein the electrical connection layer(12a, ¶0018) is a metal silicide(¶0058).
Regarding claim 4, Kono teaches the electronic device according to claim 1, wherein the electrical connection layer(12a, ¶0018) extends on the surface(P1, ¶0021) of the semiconductor body(10, ¶0020) in direct contact with the source region(30, ¶0031) at the second electrical contact region(CP1, ¶0033).
Regarding claim 5, Kono teaches the electronic device according to claim 1, wherein the semiconductor body(10, ¶0020) is Silicon Carbide (SiC)(¶0020).
Regarding claim 6, Kono teaches a method of manufacturing(Fig. 1) an electronic device, comprising:
forming, in a semiconductor body(10, ¶0020) having a surface(P1, ¶0021), a body region(28, ¶0025) which extends along a first direction parallel to the surface(P1, ¶0021) of the semiconductor body(10, ¶0020), and a source region(30, ¶0031) which extends in the body region(28, ¶0025) along the first direction;
forming, in the semiconductor body(10, ¶0020) at the body and source regions(28, 30, ¶0025, ¶0031), a first and a second electrical contact region(CP1, CP2, ¶0033, ¶0037) alternating with each other along the first direction, by forming a plurality of trenches(22a, 22b, ¶0018, trench between adjacent 20a) at the first electrical contact region(CP2,CP3, ¶0037, ¶0042) that expose the body region(28, ¶0025), and
forming a plurality of raised portions(CP1, ¶0031) alternating between the trenches(22a, 22b, ¶0018) at the second electrical contact region(CP1, ¶0033) that expose the source region(30, ¶0031);
forming an electrical connection layer(12a, ¶0018) which extends with electrical continuity longitudinally to the body and source regions(28, 30, ¶0025, ¶0031), in electrical connection with the first and second electrical contact regions(CP1, CP2, ¶0033, ¶0037),
forming a gate dielectric(16a, ¶0018) on the surface of the semiconductor body(10, ¶0020);
forming a gate terminal(18a, ¶0018) on a first portion(top portion) of the gate dielectric(16a, ¶0018);
an L-shaped dielectric layer(20a, ¶0018, please see examiner annotated Fig. 1) a second portion(side portion) of the gate dielectric(16a, ¶0018) and the gate terminal(18a, ¶0018).
Regarding claim 7, Kono teaches the method according to claim 6, further comprising:
forming a first trench(trench between adjacent 20a) of the plurality of trenches(22a, 22b, ¶0018, trench between adjacent 20a) through the dielectric layer(20a, ¶0018) at the source region(30, ¶0031), exposing a corresponding portion of the surface(P1, ¶0021) of the semiconductor body(10, ¶0020) at the source region(30, ¶0031) faced thereto,
wherein forming the first electrical contact region(CP2,CP3, ¶0037, ¶0042) includes forming, within the first trench(trench between adjacent 20a), a second trench(22a, 22b, ¶0018) of the plurality of trenches(22a, 22b, ¶0018, trench between adjacent 20a) in the semiconductor body(10, ¶0020) from the surface(P1, ¶0021), the second trench(22a, 22b, ¶0018) extending completely through the source region(30, ¶0031) and ending within the body region(28, ¶0025).
Regarding claim 10, Kono teaches the method according to claim 6, wherein the electrical connection layer(12a, ¶0018) is formed superimposed, in top-plan view, on the source and body regions(28, 30, ¶0025, ¶0031).
Regarding claim 12, Kono teaches a device(Fig. 1), comprising:
a semiconductor layer(10, ¶0020);
a body region(28, ¶0025) of a first conductivity type(P) in the semiconductor layer(10, ¶0020);
a plurality of source regions(30, ¶0031) of a second conductivity type(N) spaced from each other along a first direction;
a plurality of first openings(22a, 22b, ¶0047) through the source region(30, ¶0031) that expose portions of the body region(28, ¶0025);
a gate electrode(16a, 18a, ¶0018) that overlaps the body region(28, ¶0025) and the plurality of source regions(30, ¶0031), the gate electrode(18a, ¶0018) including:
a gate dielectric(16a, ¶0018) covering the semiconductor layer(10, ¶0020), the body region(28, ¶0025), and the plurality of source regions(30, ¶0031); and
a gate conductive terminal(18a, ¶0018) on a first portion of the gate dielectric(16a, ¶0018);
a second opening(space between adjacent 20a, ¶0018) in the gate electrode(18a, ¶0018) that exposes the plurality of source regions(30, ¶0031) and the portions of the body region(28, ¶0025), the second opening(space between adjacent 20a, ¶0018) having a first dimension(width of space between adjacent 20a) in the first direction and a second dimension(height of 20a) in a second direction that is transverse to the first direction;
a first insulating layer(20a, ¶0018) has a first portion on the gate conductive terminal(18a, ¶0018) and a second portion on a second portion of the gate dielectric(16a, ¶0018), the second portion of the first insulating layer(20a, ¶0018) forming a sidewall of the second opening(space between adjacent 20a, ¶0018); and
a connection electrode(12a, ¶0018) that is in the second opening(space between adjacent 20a, ¶0018), in contact with the portions of the body region(28, ¶0025), and in contact with the plurality of source regions(30, ¶0031).
Regarding claim 18, Kono teaches the device of claim 12, wherein a first of the plurality of source regions(30, ¶0031) is partially overlapping the gate conductive terminal(18a, ¶0018) along the second direction.
Regarding claim 20, Kono teaches the device of claim 12, wherein each of the plurality of source regions(30, ¶0031) extends a first depth(depth of 30) into the semiconductor layer(10, ¶0020) along the second direction and the plurality of first openings(22a, 22b, ¶0047) has a second depth(depth of 22a, 22b) into the semiconductor layer(10, ¶0020) along the second direction greater than the first depth(depth of 30).
Regarding claim 21, Kono teaches the device of claim 12, wherein the first insulating layer(20a, ¶0018) entirely covers a first surface and a first sidewall of the gate conductive terminal(18a, ¶0018).
Regarding claim 22, Kono teaches the device of claim 12, wherein the body region(28, ¶0025) is partially overlapped with the gate conductive terminal(18a, ¶0018) along the second direction.
Claims 1-2, 6-8, 10, 12-15, 18-22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nagakura et al. (US 2020/0381551 A1) of record.
Regarding claim 1, Nagakura teaches an electronic device(Fig. 4), comprising:
a semiconductor body(2, ¶0025) having a surface(2a, ¶0025);
a body region(14, 16, ¶0045) in the semiconductor body(2, ¶0025), extending along a first direction parallel to the surface(2a, ¶0025) of the semiconductor body(2, ¶0025); and
a source region(15, ¶0045) in the body region(14, 16, ¶0045), extending along the first direction(X),
a gate dielectric(17, ¶0046) on the surface of the semiconductor body(2, ¶0025);
a gate terminal(11, ¶0064) on the gate dielectric(17, ¶0046);
an L-shaped gate dielectric(31, ¶0067, please see examiner annotated Fig. 4) directly on both the gate dielectric(17, ¶0046) and the gate terminal(11, ¶0064),
a plurality of trenches(60, 45, ¶0065-66) through the source region(15, ¶0045) and extending into the body region(14, 16, ¶0045);
a plurality of raised regions(15, ¶0045) alternating with each trench of the plurality of trenches(60, 45, ¶0065-66), each raised region being on the source region(15, ¶0045);
a first electrical contact region(16, ¶0045) in each trench;
a second electrical contact region(15, ¶0045) on each raised region(15, ¶0045);
an electrical connection layer(20, ¶0053) extending with electrical continuity longitudinally to the body and source regions(14, 16, 15, ¶0064), in electrical connection with the first and second electrical contact regions(16, 15, ¶0045) in the plurality of trenches(60, 45, ¶0065-66) and on the plurality of raised regions(15, ¶0045).
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Regarding claim 2, Nagakura teaches the electronic device according to claim 1, wherein the first and second electrical contact regions(16, 15, ¶0045) are contiguous to each other along the first direction(X).
Regarding claim 6, Nagakura teaches a method of manufacturing an electronic device(Fig. 5), comprising:
forming, in a semiconductor body(2, ¶0025) having a surface(2a, ¶0025), a body region(14, 16, ¶0064) which extends along a first direction parallel to the surface(2a, ¶0025) of the semiconductor body(2, ¶0025), and a source region(15, ¶0064) which extends in the body region(14, 16, ¶0064) along the first direction;
forming, in the semiconductor body(2, ¶0025) at the body and source regions(14, 16, 15, ¶0064), a first and a second electrical contact region(16, 15, ¶0064) alternating with each other along the first direction, by forming a plurality of trenches(60, 45, ¶0065-66) at the first electrical contact region(16, ¶0064) that expose the body region(14, 16, ¶0064), and forming a plurality of raised portions alternating between the trenches(60, 45, ¶0065-66) at the second electrical contact region(15, ¶0064) that expose the source region(15, ¶0064);
forming an electrical connection layer(20, ¶0053) which extends with electrical continuity longitudinally to the body and source regions(14, 16, 15, ¶0064), in electrical connection with the first and second electrical contact regions(16, 15, ¶0064);
forming a gate dielectric(17, ¶0046) on the surface of the semiconductor body(2, ¶0025);
forming a gate terminal(11, ¶0064) on a first surface of the gate dielectric(17, ¶0046);
and forming an L-shaped gate dielectric layer(31, ¶0067, please see examiner annotated Fig. 4) on a second portion of the gate dielectric(17, ¶0046) and the gate terminal(11, ¶0064)
Regarding claim 7, Nagakura teaches the method according to claim 6, further comprising:
forming a first trench(45, ¶0052) of the plurality of trenches(60, 45, ¶0065-66) through the dielectric layer(31, ¶0067) at the source region(15, ¶0064), exposing a corresponding portion of the surface(2a, ¶0025) of the semiconductor body(2, ¶0025) at the source region(15, ¶0064),
wherein forming the first electrical contact region(16, ¶0064) includes forming, within the first trench(45, ¶0052), a second trench(45, ¶0066) of the plurality of trenches(60, 45, ¶0065-66) in the semiconductor body(2, ¶0025) from the surface(2a, ¶0025), the second trench(45, ¶0066) extending completely through the source region(15, ¶0064) and ending within the body region(14, 16, ¶0064).
Regarding claim 8, Nagakura teaches the method according to claim 7, further comprising, prior to forming the second trench(45, ¶0066), forming an etching mask(32, ¶0065, ¶0067) which extends into the first trench(45, ¶0052) covering the second electrical contact region(15, ¶0064) and leaving the first electrical contact region(16, ¶0064) uncovered.
Regarding claim 10, Nagakura teaches the method according to claim 6, wherein the electrical connection layer(20, ¶0053) is formed superimposed, in top-plan view, on the source and body regions(14, 16, 15, ¶0064).
Regarding claim 12, Nagakura teaches a device(Fig. 4), comprising:
a semiconductor layer(2, ¶0025);
a body region(14, 16, ¶0064) of a first conductivity type(P) in the semiconductor layer(2, ¶0025);
a plurality of source regions(15, ¶0064) of a second conductivity type(N) spaced from each other along a first direction;
a plurality of first openings(45, ¶0052) through the source region(15, ¶0064) that expose portions of the body region(14, 16, ¶0064);
a gate electrode(11, 12, ¶0064, ¶0034, Fig. 2) that overlaps the body region(14, 16, ¶0064) and the plurality of source regions(15, ¶0064), the gate electrode includes:
a gate dielectric(17, ¶0046) covering the semiconductor layer(2, ¶0025), the body region(14, 16, ¶0064) and the plurality of source regions(15, ¶0064) and;
a gate conductive terminal(11, ¶0064) on a first portion of the gate dielectric(17, ¶0046);
a second opening(40, ¶0052) in the gate electrode(11, ¶0064) that exposes the plurality of source regions(15, ¶0064) and the portions of the body region(14, 16, ¶0064), the second opening(40, ¶0052) having a first dimension(width of 40) in the first direction(X) and a second dimension(length of 40) in a second direction(Y) that is transverse to the first direction(Y);
a first insulating layer(31, ¶0067) has a first portion on the gate conductive layer and a second portion on a second portion on the gate dielectric(17, ¶0046) the second portion of the first insulating layer(31, ¶0067) forming a sidewall of the second opening(40, ¶0052);
a connection electrode(20, ¶0068) that is in the second opening(40, ¶0052), in contact with the portions of the body region(14, 16, ¶0064) and in contact with the plurality of source region(15, ¶0064).
Regarding claim 13, Nagakura teaches the device of claim 12, comprising a second insulating layer(32, ¶0067) on sidewalls of the first insulating layer(31, ¶0067) and in the second opening(40, ¶0052).
Regarding claim 14, Nagakura teaches the device of claim 13 wherein the connection electrode(20, ¶0068) is between opposing sides of the second insulating layer(32, ¶0067).
Regarding claim 15, Nagakura teaches the device of claim 14 wherein the gate dielectric(17, ¶0046) entirely separates the gate conductive terminal(11, 12, ¶0064, ¶0034, Fig. 2) from the body region(14, 16, ¶0064) and the gate conductive terminal(11, 12, ¶0064, ¶0034, Fig. 2) from the plurality of source regions(15, ¶0064).
Regarding claim 18, Nagakura teaches the device of claim 12, wherein a first of the plurality of source regions(15, ¶0064) is partially overlapping the gate conductive terminal(11, 12, ¶0064, ¶0034, Fig. 2) along the second direction.
Regarding claim 19, Nagakura teaches the device of claim 18, wherein a side of the second portion of the gate dielectric(17, ¶0046) is with a side of the first of the plurality of source regions(15, ¶0064) along the second direction.
Regarding claim 20, Nagakura teaches the device of claim 12, wherein each of the plurality of source regions(15, ¶0064) extends a first depth(depth of 15) into the semiconductor layer(2, ¶0025) along the second direction and the plurality of first openings(45, ¶0052) has a second depth(depth of 45) into the semiconductor layer (2, ¶0025) along the second direction greater than the first depth(depth of 15).
Regarding claim 21, Nagakura teaches the device of claim 12, wherein the first insulating layer(31, ¶0067) entirely covers a first surface(top surface) and a first sidewall of the gate conductive terminal(11, 12, ¶0064, ¶0034, Fig. 2).
Regarding claim 22, Nagakura teaches the device of claim 12, wherein the body region(14, 16, ¶0064) is partially overlapped with the gate conductive terminal(11, 12, ¶0064, ¶0034, Fig. 2) along the second direction.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 9 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Kono et al. (US 2017/0271467 A1) in view of Tsui et al. (US 2024/0096981 A1) both of record.
Regarding claim 9, Kono teaches the method according to claim 7, wherein the semiconductor body(10, ¶0020) includes Silicon(¶0020).
Kono does not explicitly state forming the electrical connection layer(12a, ¶0018) includes: depositing a metal layer within the first and the second trenches(trench between adjacent 20a, 22a, 22b, ¶0018,) at the first and the second electrical contact regions(CP1, CP2, ¶0033, ¶0037), and carrying out a thermal process for forming a Silicide of the metal layer. Kono does teach the electrical connection layer(12a, ¶0018) is a metal silicide(¶0058).
Tsui teaches a method of manufacturing an electronic device(Fig. 7-12) wherein forming the electrical connection layer(130, ¶0059) includes: depositing a metal layer(Ni, ¶0059) within the first and the second trenches(WD, Fig. 8, WD) at the first and the second electrical contact regions(601, 602, 800, ¶0059), and carrying out a thermal process for forming a Silicide(Ni-silicide, ¶0059) of the metal layer(Ni, ¶0059). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Kono, forming the electrical connection layer includes: depositing a metal layer within the first and the second trenches at the first and the second electrical contact regions, and carrying out a thermal process for forming a Silicide of the metal layer, as taught by Tsui, in order to form a step-like three-dimensional structure(¶0059).
Regarding claim 11, Kono teaches the method according to claim 10, but is not relied on to teach, after forming a first trench(trench between adjacent 20a) of the plurality of trenches(trench between adjacent 20a), depositing a protection layer of insulating material along lateral walls of the first trench(trench between adjacent 20a).
Tsui teaches a method of manufacturing an electronic device(Fig. 7-12) wherein after forming a first trench(WD, Fig. 8) of the plurality of trenches, depositing a protection layer of insulating material(190, ¶0056) along lateral walls of the first trench(WD, Fig. 8). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Kono, so that after forming a first trench of the plurality of trenches, depositing a protection layer of insulating material along lateral walls of the first trench, as taught by Tsui, in order to significantly reduce the difficulty and complexity of the current lithography etching process and to form the source metal having the step-like coverage and outline shape(¶0060).
Response to Arguments
Applicant's arguments filed 3/19/2026 have been fully considered but they are not persuasive.
Applicant's arguments fail to comply with 37 CFR 1.111(b) because they amount to a general allegation that the claims define a patentable invention without specifically pointing out how the language of the claims patentably distinguishes them from the references.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAURA DYKES whose telephone number is (571)270-3161. The examiner can normally be reached M-F 9:30 am-5 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at 571-272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LAURA M DYKES/Examiner, Art Unit 2892
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