DETAILED ACTION
This Office Action is in response to Applicant’s application 18/471,246 filed on September 20, 2023 in which claims 1 to 20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings submitted on September 20, 2023 have been reviewed and accepted by the Examiner.
Information Disclosure Statement
The Information Disclosure Statements (IDS), filed on September 20, 2023; January 18, 2024; September 10, 2024 and August 21, 2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosed therein has been considered by the Examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4, 8 and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. 2022/0208669 (Li).
Regarding claim 1 and referring to annotated Figure 2, Li discloses a semiconductor package comprising:
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a first die, 30 [0045];
a second die, 30 [0045], arranged horizontally to the first die, as shown;
a printed circuit board (PCB) layer, 10 [0044] described as including a laminate build up substrate, comprising a circuit, e.g., vias, through holes, etc. [0044], and a PCB pillar, 31 [0085], extending upwards from the circuit, as shown, so as to abut the first die or the second die, as shown; and
a connecting structure, 20 [0094], disposed on an upper surface of the PCB layer, as shown, between two different PCB pillars, as annotated and shown, and conductively connected to each of the first die and the second die, as shown and described throughout.
Regarding claim 4 which depends upon claim 1, Li discloses the connecting structure comprises a connecting pillar, 31 [0085] as annotated, disposed on an upper surface of the connecting structure, 20 as shown, so as to abut the first die or the second die, 30 as shown.
Regarding claim 8 which depends upon claim 1, Li teaches a connecting pillar, 31 [0085] as annotated, is formed on an upper surface of the connecting structure, as shown, so as to extend upwards and to abut the first die or the second die, as shown, and the connecting pillar and the PCB pillar have respective upper ends positioned on a straight line horizontally, as shown where it appears the upper ends of PCB pillar and connecting structure pillar are co-planer, hence co-linear.
Regarding claim 14 which depends upon claim 1, Li teaches at [0048] the interconnect device is formed with bond pads, not shown and at [0059, 64] teaches the connecting structure is made of a silicon wafer.
Claims 1, 4 and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. 2019/0051633 (Bhagavat).
Regarding claim 1 and referring to annotated Figure 2, Bhagavat discloses a semiconductor package comprising:
a first die, 19 [0066];
a second die, 20 [0066], arranged horizontally to the first die, as shown;
a printed circuit board (PCB) layer, 15 [0067], and a PCB pillar, 110 /115 [0066,80], extending upwards from the circuit, as shown, so as to abut the first die or the second die, as shown; and
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a connecting structure, 90 [0066], disposed on an upper surface of the PCB layer, as shown, between two different PCB pillars, as annotated and shown, and conductively connected to each of the first die and the second die, as shown.
Regarding claim 4 which depends upon claim 1, Bhagavat teaches the connecting structure comprises a connecting pillar, 150 [0068] see also Figure 3, disposed on an upper surface of the connecting structure, as shown, so as to abut the first die or the second die, as shown.
Regarding claim 8 which depends upon claim 1, Bhagavat teaches a connecting pillar, 150 [0068], is formed on an upper surface of the connecting structure, as shown, so as to extend upwards and to abut the first die or the second die, as shown, and the connecting pillar and the PCB pillar have respective upper ends positioned on a straight line horizontally where it appears that the upper ends of the respective pillars are co-planar and hence connected a straight horizontal line.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
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4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Bhagavat.
Regarding claim 3 which depends upon claim 1, Bhagavat suggests at Figure 1 the connecting structure, less than the full width of the first and second die and disposed between the die, has a sectional area formed to be smaller than the combined sectional area of the first die and the second die coupled to the connecting structure.
Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Li.
Regarding claim 6 which depends upon claim 4, Li suggests at annotated Figure 2 the height of the connecting pillar formed on the connecting structure is formed to be smaller than the sum of the horizontal thickness of the connecting pillar and the interval between two connecting pillars adjacent to each other horizontally, i.e. the pitch of the PCB pillars is greater than the height of the connecting pillars.
Regarding claim 7 which depends upon claim 4, Li suggests the height of the connecting pillar corresponds to 50-150% of the height of the connecting structure.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Li and U.S. 2023/0411348 (Hanna).
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Regarding claim 15 which depends upon claim 1, Li does not teach the connecting structure is made of an active die or an integrated passive device (IPD).
Hanna is directed to side by side dies integrated with a connecting structure, see Figure 7F where 116 [0076] is the connecting structure. At [0076], Hanna teaches that eh die 116 may comprise a bridge die without any active circuitry or may comprise active circuitry that function together with the circuitry of the attached die 102. An artisan would recognize that decoupling capacitors are used to support active die circuity to ensure stable voltage supply to the die thus improving signal integrity and improved bandwidth. Further decoupling capacitors are useful to mitigate the effect of high frequency noise on device operation.
Accordingly, it would have been obvious to a person of ordinary skill in the art at the time of Applicant’s invention to configure the device of claim 1 wherein the connecting structure is made of an active die, as taught by Hanna, or an integrated passive device (IPD) to maximize the performance of the first and second die.
Allowable Subject Matter
Claims 2, 5, 9-13 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2 the prior art fails to disclose the device of claim 1, wherein a connecting pillar is formed on an upper surface of the connecting structure so as to extend upwards with an increasing horizontal width and to abut the first die or the second die.
Regarding claim 5 the prior art fails to disclose the device of claim 4, wherein the sum of the height of the connecting structure and the height of the connecting formed on the connecting structure is formed to be smaller than the sum of the horizontal thickness of the PCB pillars and the interval between two PCB pillars, as annotated, adjacent to each other horizontally.
Regarding claim 9 the prior art fails to disclose the device of claim 1, wherein a plurality of second dies are arranged side by side horizontally, and the connecting structure has at least a part conductively connected to each of a plurality of different second dies.
Claims 10-12 depend directly or indirectly on claim 9 and are allowable on that basis.
Regarding claim 13 the prior art does not teach the device claim 1, wherein a plurality of first dies are formed to be vertically stacked.
Regarding claim 16 the prior art does not teach the device claim 1, wherein a plurality of PCB pillars and connecting pillars are disposed on an upper surface of the PCB layer to be spaced apart from each other, the plurality of PCB pillars and connecting pillars are formed at an identical height, and assuming that the PCB layer has a transverse length of Lx and has a longitudinal length of Ly, the PCB pillars and connecting pillars have transverse coordinates of xi and have longitudinal coordinates of yi, and pad area of the PCB pillars or connecting pillars formed and exposed on the PCB layer is Ai, equations
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are both satisfied.
Claims 17-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 17 the prior art fails to disclose a semiconductor package manufacturing method comprising the steps of: (a) forming a PCB pillar so as to extend upwards from a circuit of a PCB layer; (b) installing a connecting structure between two different PCB pillars; (c) forming a mold on the PCB layer and the connecting structure; (d) grinding the mold such that the upper end of the PCB pillar and the upper end of a connecting pillar extending upwards from the connecting structure are exposed outwards; and (e) installing a first die and a second die side by side horizontally on the upper end of the PCB layer and on the upper end of the connecting pillar such that each of the first die and the second die contact the connecting pillar conductively.
Claims 18-20 depend directly or indirectly on claim 17 and are allowable on that basis.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure is listed on the notice of references cite.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Joe Schoenholtz whose telephone number is (571)270-5475. The examiner can normally be reached M-Thur 7 AM to 7 PM PST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ms. Yara Green can be reached at (571) 272-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/J.E. Schoenholtz/Primary Examiner, Art Unit 2893