Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. DETAILED ACTION This office action is in response to the Applicant Election filled on 01/22/2026 . Currently, claims 1- 18 are pending in the application . Claims 9-12 and 14 have been withdrawn from consideration. Election /Restrictions Applicant's election without traverse of Species IV (Figures 5A-5B ), claims 1-8, 13 and 15-18 , in the reply filed on 01/22/2026 is acknowledged, there being no allowable generic or linking claim. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1 -2 , 5-8 and 15-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Higashitani et al ( US 20130130468 A1 ) . Regarding claim 1, Figure s 1B, 2B, 8, 28A and 29A of Higashitani disclose a capacitor structure (Figure 29A) , comprising: a substrate (190, [0066]) , having a capacitor array region ( middle portion in Figure 29A ) and a capacitor staircase region ( peripheral region in Figure 28A/29A , [0176]) ; a circuit under array structure (2918 , [0184] ) , disposed on the substrate; a bottom conductive layer (L1 , [0183] ) , disposed on the circuit under array structure (2918) ; a stacked structure (L2-L13, [0183]) , disposed on the bottom conductive layer, and comprises a plurality of first dielectric layers (L2/L4/L6/L8/L10/L12 , [0183] ) and a plurality of conductive layers (L3/L5/L7/L9/L11/L13 , [0183] ) stacked alternately, wherein the plurality of conductive layers in the capacitor staircase region are arranged in a staircase form (L1-L13 forms a staircase on both side in Figure 29A ) ; and a plurality of pillar structures ( H1-H8, Figure 8) , arranged in an array and penetrating through the stacked structure and the bottom conductive layer (L1) in the capacitor array region (CA3/CA4, [0096]) , wherein a part of the plurality of conductive layers ( L3/L7/L11 ) is electrically connected to a first common voltage source (2902, [0183]) , and the rest of the plurality of conductive layers (L1/L5/L9/L13) and the bottom conductive layer are electrically connected to a second common voltage source (2904, [0183] , terminal of capacitors are connected to two different input voltage ) . Regarding claim 2 , Figures 1B, 2B, 8, 28A and 29A of Higashitani disclose that the capacitor structure according to claim 1, wherein the part of the conductive layers comprises odd-numbered conductive layers (3 layers connected to 2902 , Figure 29A ) of the plurality of conductive layers, and the rest of the plurality of conductive layers comprises even-numbered conductive layers (4 layers are connected to 2904 , Figure 29A ) of the plurality of conductive layers. Regarding claim 5 , Figure s 1B, 2B, 3-5, 8 and 28-29 of Higashitani disclose that the capacitor structure according to claim 1, wherein one conductive layer connected to the first common voltage source, an adjacent conductive layer connected to the second common voltage source, and the first dielectric layer therebetween constitute a capacitance unit (Figure29A) . Regarding claim 6 , Figures 1B, 2B, 8, 28A and 29A of Higashitani disclose that the capacitor structure according to claim 1, further comprising a plurality of conductive pillars (2802-2814) , located in the capacitor staircase region, and disposed on the plurality of conductive layers and the bottom conductive layer (L1) , so that the plurality of conductive layers and the bottom conductive layer are electrically connected to the corresponding common voltage sources through the plurality of conductive pillars (Figure 29A) . Regarding claim 7 , Figures 1B, 2B, 8, 28A and 29A of Higashitani disclose that the capacitor structure according to claim 1, wherein each of the plurality of pillar structures (H1-H8 , Figure 8 ) comprises a first insulating pillar ( one of the ONO layer in memory holes, [ 0098 ]) . Regarding claim 8 , The capacitor structure according to claim 7, wherein each of the plurality of pillar structures further comprises a second insulating pillar disposed in the first insulating pillar ( another one of ONO layer in memory holes, [0098]) . Regarding claim 1 5 , Figures 1B, 2B, 8, 28A and 29A of Higashitani disclose that the capacitor structure according to claim 1, wherein the bottom conductive layer and the stacked structure have a plurality of second annular trenches (S2-S8, [0106]) , each of the plurality of second annular trenches penetrates through the bottom conductive layer (L1) and the stacked structure, and each of the plurality of second annular trenches extends along a row direction of the capacitor array region and surrounds at least one row of the pillar structures (Hs) and the stacked structure in the capacitor staircase region, so as to form an independent bottom conductive sector (Slits are separating the stacked structure in the capacitor staircase region, Figure 8) . Regarding claim 16, Figures 1B, 2B, 8, 28A and 29A of Higashitani disclose that the capacitor structure according to claim 15, further comprising second dielectric layers (in region IA1, Figure 8) disposed between adjacent conductive sectors, located between the first dielectric layers and corresponding to locations of the conductive layers in a stacking direction of the stacked structure (Figures 7-11 teaches that the middle region having two dielectric layers alternating but one of the dielectric layers is replaced to form the conductive layers in the CA3/CA4 regions, [0103]) . Regarding claim 1 7 , Figures 1B, 2B, 8, 28A and 29A of Higashitani disclose that the capacitor structure according to claim 16, wherein the second dielectric layers (in regions IA1 , Figure 8) are disposed between the conductive layers of the adjacent conductive sectors (CA3/CA4) . Regarding claim 1 8 , Figures 1B, 2B, 8, 28A and 29A of Higashitani disclose that the capacitor structure according to claim 16, wherein a material of the second dielectric layers is different from a material of the first dielectric layers ([0086] and [0126], Figures 7-11) . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 3 -4 are rejected under 35 U.S.C. 103 as being obvious over Higashitani et al ( US 20130130468 A1 ) . Regarding claim s 3 -4 , Figures 1B, 2B, 8, 28A and 29A of Higashitani do not explicitly teach that the capacitor structure according to claim 1, wherein at least a pair of adjacent conductive layers is electrically connected to the first common voltage source or the second common voltage source. Or The capacitor structure according to claim 1, wherein the bottom conductive layer and a lowermost conductive layer of the plurality of conductive layers are electrically connected to the first common voltage source or the second common voltage source. However, Figures 31A-31F teaches of connecting adjacent conductive layers for forming a combination of passive device such as capacitor and resistor for allow ing two types of passive devices to be fabricated in the same area of the substrate, providing flexibility and space-efficiency ([0201]) . Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to use the claimed arrangement in the device of Higashitani in order to form two types of passive devices to be fabricated in the same area of the substrate, providing flexibility and space-efficiency ([0201] of Higashitani ). Claim 13 is rejected under 35 U.S.C. 103 as being obvious over Higashitani et al ( US 20130130468 A1 ) in view of KIM et al ( US 20190221579 A1 ) . Regarding claim 13, Higashitani does not teach that the capacitor structure according to claim 1, wherein the circuit under array structure further comprises a metal oxide semiconductor capacitor. However, KIM is a pertinent art which teaches each of the cell strings CSTR of FIG. 2 includes one of the channel structures VS1 and VS2, the stacked structure 100, and one of the selection structures SS1 and SS2. The channel structures VS1 and VS2 may constitute metal-oxide-semiconductor field effect transistors (MOSFET) using the channel structures VS1 and VS2 as channel regions thereof, along with the lower, cell, and selection conductive patterns 110G, 110, and 110S. Alternatively, the channel structures VS1 and VS2 may constitute metal-oxide-semiconductor (MOS) capacitors, along with the lower, cell, and selection conductive patterns 110G, 110, and 110S ([0058] , Figures 1-5 ) . Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to use a metal oxide semiconductor capacitor instead of metal-oxide-semiconductor field effect transistors (MOSFET) in the circuit under array structure (2918, [0184]) of Higashitani according to the teaching of KIM in order to use with channel structure in the memory string for higher integration and lower cost, and further the court has held that a simple substitution of one known element for another to obtain predictable results is obvious. KSR Int'l v. Teleflex Inc., 127 S.Ct. 1727 (2007) . Examiner Notes A reference to specific paragraphs, columns, pages, or figures in a cited prior art reference is not limited to preferred embodiments or any specific examples. It is well settled that a prior art reference, in its entirety, must be considered for all that it expressly teaches and fairly suggests to one having ordinary skill in the art. Stated differently, a prior art disclosure reading on a limitation of Applicant's claim cannot be ignored on the ground that other embodiments disclosed were instead cited. Therefore, the Examiner's citation to a specific portion of a single prior art reference is not intended to exclusively dictate, but rather, to demonstrate an exemplary disclosure commensurate with the specific limitations being addressed. In re Heck, 699 F.2d 1331, 1332-33,216 USPQ 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 USPQ 275, 277 (CCPA 1968)). In re: Upsher-Smith Labs. v. Pamlab, LLC, 412 F.3d 1319, 1323, 75 USPQ2d 1213, 1215 (Fed. Cir. 2005); In re Fritch, 972 F.2d 1260, 1264, 23 USPQ2d 1780, 1782 (Fed. Cir. 1992); Merck& Co. v. BiocraftLabs., Inc., 874 F.2d 804, 807, 10 USPQ2d 1843, 1846 (Fed. Cir. 1989); In re Fracalossi, 681 F.2d 792,794 n.1, 215 USPQ 569, 570 n.1 (CCPA 1982); In re Lamberti, 545 F.2d 747, 750, 192 USPQ 278, 280 (CCPA 1976); In re Bozek, 416 F.2d 1385, 1390, 163 USPQ 545, 549 (CCPA 1969). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT KHAJA AHMAD whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-7991 . The examiner can normally be reached on FILLIN "Work schedule?" \* MERGEFORMAT Monday-Friday, 8:00 AM - 5:00 PM (Eastern Time). If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, GAUTHIER STEVEN B, can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300 . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice . Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KHAJA AHMAD/ Primary Examiner, Art Unit 2813