DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
2. The information disclosure statement (IDS) submitted on June 14, 2024 has been fully considered by the examiner.
Election/Restrictions
3. Claims 17 and 19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim.
Election was made without traverse in the reply filed on April 2, 2026.
Specification
4. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “Memory Device with Non-uniform Bonding Pad Spacing.”
Claim Objections
5. Claim 3 is objected to because of the following informalities: Lines 2-3 recite “pager buffer region,” which should read “page buffer region.” Appropriate correction is required.
Claim Rejections - 35 USC § 112
6. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
7. Claims 3, 11-12, 16, 18, and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 recites the limitation “the corresponding first bonding pads” in line 6. There is insufficient antecedent basis for this limitation in the claim. For the purpose of this action, “the corresponding first bonding pads” shall be interpreted as “[[the]] corresponding first bonding pads.”
Claim 3 recites the limitation "the corresponding second bonding pads" in line 7. There is insufficient antecedent basis for this limitation in the claim. For the purpose of this action, “the corresponding second bonding pads” shall be interpreted as “[[the]] corresponding second bonding pads.”
Claim 11 recites the limitation “the corresponding bit lines” in line 2. There is insufficient antecedent basis for this limitation in the claim. For the purpose of this action, “the corresponding bit lines” shall be interpreted as “[[the]] corresponding bit lines.” Claim 12 depends on claim 11.
Claim 16 recites the limitation “the second connection portions connecting one of the groups of first bonding pads” in lines 1-2. There is insufficient antecedent basis for this limitation in the claim. For the purpose of this action, “the second connection portions connecting one of the groups of first bonding pads” shall be interpreted as “[[the]] second connection portions connecting one of the groups of first bonding pads.”
Claim 18 recites the limitation “the first connection portions connecting one of the groups of first bonding pads” in lines 1-2. There is insufficient antecedent basis for this limitation in the claim. For the purpose of this action, “the first connection portions connecting one of the groups of first bonding pads” shall be interpreted as “[[the]] first connection portions connecting one of the groups of first bonding pads.”
Claim 20 recites the limitation “the bit lines extending over the second bonding pads” in line 2. There is insufficient antecedent basis for this limitation in the claim. For the purpose of this action, “the bit lines extending over the second bonding pads” shall be interpreted as “[[the]] bit lines extending over the second bonding pads.”
Claim Rejections - 35 USC § 103
8. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
9. Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Murakami (US 20230083442 A1) in view of Lin (US 20210202418 A1).
Regarding independent claim 1, Murakami teaches a memory device, comprising:
a substrate (¶[0003]), comprising a first region (FIG. 10, left memory block BLK; ¶[0075]) and a second region (FIG. 10, inter-block insulating layer 106; ¶[0075]) adjacent to each other (FIG. 10 shows left memory block and inter-block insulating layer adjacent to one another in the Y direction);
a bonding structure (FIG. 10, including bonding pads P.sub.x; ¶[0072]), disposed over the substrate (FIG. 10, P.sub.x shown “over” L.sub.SB), comprising:
a bonding dielectric layer (FIG. 10, insulating layer 107, 108 of C.sub.M; ¶[0093]), disposed over the substrate in the first region and the second region (FIG. 10, 107, 108 shown “over” L.sub.SB);
a plurality of first bonding pads (FIG. 10, bonding pads P.sub.11; ¶[0072]), embedded in the bonding dielectric layer over the substrate in the first region (FIG. 10, P.sub.11 shown embedded in 107, 108 of C.sub.M); and
a plurality of second bonding pads (FIG. 10, P.sub.12), embedded in the bonding dielectric layer over the substrate in the second region (FIG. 10, P.sub.12 shown embedded in 107, 108 of C.sub.P); and
a plurality of bit lines (FIG. 10, 140 extending in the Y direction; ¶[0088] teaches “wiring layer 140 includes a plurality of wirings 141…Some of the plurality of wirings 141 function as the bit lines BL”; see also FIG. 9, 140), disposed over the bonding structure (FIG. 10 shows 140 “over” the bonding pads), the bit lines extending from the first region to the second region (FIG. 10, 140 shown extending across BLK and 106), wherein each of the first bonding pads is electrically connected to one of the bit lines (e.g., BL is shown connected to P.sub.11; see also FIG. 9; ¶[0047] teaches sense amplifier module SAM is on the peripheral chip (C.sub.P), which indicates each BL must be coupled to the peripheral chip).
Murakami does not teach a density of the first bonding pads in the first region is greater than a density of the second bonding pads in the second region (see, e.g., FIG. 6, in which the densities of bonding pads in the memory blocks and inter-block regions appear similar).
Lin teaches outer bonding pads may have higher density than inner bonding pads (e.g., FIG. 6, ¶[0047-0048]).
Therefore, Murakami as modified by Lin teaches a density of the first bonding pads in the first region is greater than a density of the second bonding pads in the second region (Murakami FIGS. 6-7 show memory blocks BLK closer to the periphery of chip C.sub.M than the inter-block insulating region, so the inter-block insulating region may be considered an “inner bonding pads” area requiring fewer bonding pads per Lin).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Lin into the method of Murakami to include a higher density of outer bonding pads. The ordinary artisan would have been motivated to modify Murakami in the above manner for the purpose of enhancing the mechanical strength and bonding strength in the periphery of the chip (Lin ¶[0048]).
10. Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Murakami (US 20230083442 A1) in view of Lin (US 20210202418 A1) and further in view of Yabe (US 20220406364 A1).
Regarding claim 2, Murakami as modified by Lin teaches the limitations of claim 1.
Murakami further teaches the second region comprises a second sub-region of the memory array region overlapping with a peripheral circuit region (FIG. 10, inter-block insulating layer 106 shown overlapping peripheral region residing on C.sub.P; note the full memory array region comprises multiple blocks and inter-block insulating regions).
Murakami does not teach the first region comprises a first sub-region of a memory array region overlapping with a page buffer region (note, however, in FIGS. 9-10, bit lines are routed to circuitry immediately below first region BLK, and ¶[0047] teaches sense amplifier module SAM is on C.sub.P).
Yabe teaches the first region comprises a first sub-region of a memory array region overlapping with a page buffer region (FIG. 5B; ¶[0140] teaches “peripheral circuitry 504 may include…page buffers, sense amplifiers...” and ¶[0141] teaches “the peripheral circuitry can be hidden underneath the array, referred to as CMOS under array (CUA),” thereby teaching overlapping of a memory array region with a page buffer region).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Yabe into the method of Murakami to include page buffers into peripheral circuitry underneath a memory array. The ordinary artisan would have been motivated to modify Murakami in the above manner for the purpose of overcoming the issue of peripherals taking up too large an area and too high a percentage of the total die size as memory scales (Yabe ¶[0141]).
Regarding claim 3, Murakami as modified by Lin and Yabe teaches the limitations of claim 2.
Murakami further teaches a plurality of third bonding pads, disposed in the bonding dielectric layer in the pager buffer region (FIGS. 9-10; i.e., bonding pads P.sub.12 on C.sub.P coupled to BL through P.sub.11 on C.sub.M); and
a plurality of fourth bonding pads, disposed in the bonding dielectric layer in the decoder region (¶[0047] teaches a row decoder (FIG. 4, RD) is on C.sub.P) and the peripheral circuit region (i.e., bonding pads P.sub.12 on C.sub.P other than those coupled to BL),
wherein the third bonding pads are bonded to the corresponding first bonding pads (i.e., “third bonding pads” P.sub.12 on C.sub.P coupled to BL through “first bonding pads” P.sub.11 on C.sub.M), and the fourth bonding pads are bonded to the corresponding second bonding pads (FIG. 9, RD on C.sub.P coupled to word lines 110 (¶[0077]) though “fourth bonding pads” P.sub.12 on C.sub.P and “second bonding pads” P.sub.11 on C.sub.M).
Allowable Subject Matter
11. Claims 4-16, 18, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
12. The following is a statement of reasons for the indication of allowable subject matter.
Regarding claim 4, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach or suggest the claimed limitation of the first bonding pads are arranged in a first array, the second bonding pads are arranged in a second array, and an arrangement of the first array is different from an arrangement of the second array. Claims 5-16, 18, and 20 depend on claim 4.
Citation of Relevant Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Maejima (US 20220301615 A1) teaches different bonding pad densities in different regions, but bonding pads in the bit line area are lower density instead of higher density and bit lines do not appear to reach the second region.
Chen (US 20220208705 A1) teaches different bonding pad densities in different regions, but in the direction perpendicular to bit lines, not in parallel.
Choi (US 20220320025 A1) appears to teach different bonding pad densities in different regions, but in the direction perpendicular to bit lines, not in parallel.
Lee (US 20240266308 A1) teaches bit lines in the D2 direction reaching to the second region, but the bonding pads appear uniformly spaced.
Nam (US 20240222322 A1) teaches different bonding pad densities in different regions, but does not appear to teach bit lines extending to more than one region.
Arai (US 20230411328 A1) teaches different bonding pad pitches for different regions, but the pitch appears uniform for the entire bit line area.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRADLEY COON whose telephone number is (571)270-0740. The examiner can normally be reached M-F 8am-5pm (Eastern).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, AMIR ZARABIAN can be reached at (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/B.S.C./Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
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