DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I (claim 1-15) in the reply filed on 12/24/2025 is acknowledged.
Claims 16-33 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/24/2025.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 12 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al (US Publication no. 2019/0043880)
Regarding claim 12, Lee discloses a gate structure including stacked gate lines¶0047 Fig 5A, GE; a channel structure Fig 8 ¶0077-0078 extending through the gate structure; contact plugs Fig 5A ¶0065 extending through the gate structure and connected to the gate lines Fig 5A, respectively; a dummy gate structure Fig 5A, GE d2 adjacent to the gate structure in a first direction and including stacked dummy gate lines Fig 5A; a dummy channel structure ¶0040 extending through the dummy gate structure; and an isolation insulating structure located between the gate structure and the dummy gate structure Fig 5A, extending in a second direction intersecting the first direction, and including dummy contact plugs Fig 5A, 184d arranged in the second direction.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7, 10-11, 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US Publication no. 2019/0043880) in view of Lim et al (US Publication No. 2021/0005629).
Regarding claim 1, Lee discloses a semiconductor device comprising: a gate structure ¶0047 Fig 5A, GE including gate lines and insulating layers that are alternately stacked Fig 5A; a channel structure Fig 8 ¶0077-0078 extending through the gate structure Fig 8, GE; a dummy gate structure Fig 5A, GE d2 including stacked dummy gate lines ¶0060; a dummy channel structure ¶0040 extending through the dummy gate structure Fig 5A; and an isolation insulating structure including horizontal portions stacked between the gate structure and the dummy gate structure Fig 5A. Lee discloses all the limitations but silent on the arraignment of the isolation structure. Whereas Lim discloses a semiconductor device comprising: a gate structure ¶0054 including gate lines and insulating layers that are alternately stacked Fig 14; a channel structure Fig 14, CCS¶0057 extending through the gate structure Fig 14; a dummy channel structure ¶0062 extending through the dummy gate structure Fig 14; and an isolation insulating structure Fig 14, TIP and Fig 14, 330 including horizontal portions stacked between the gate structure Fig 14 and vertical portions extending through the horizontal portions Fig 14. Lee and Lim are analogous art because they are directed to vertical memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lee because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the Lee’s device and incorporate the teachings of Lim to improve device isolation.
Regarding claim 2, Lee discloses wherein the horizontal portions are located to correspond to the gate lines and the dummy gate lines¶0060 Fig 5A.
Regarding claim 3, Lee discloses wherein the insulating layers extend between the horizontal portions and between the dummy gate lines Fig 5A.
Regarding claim 4, Lim discloses wherein the isolation insulating structure comprises: an isolation layer including the horizontal portions and the vertical portions; and a dummy contact plug located in the isolation layer Fig 14.
Regarding claim 5, Lim discloses wherein the dummy contact plug is located on the horizontal portions, and the vertical portions extend along sidewalls of the dummy contact plug Fig 14 ¶0087-0088, 0094.
Regarding claim 7, Lim discloses contact plugs extending through the gate structure and connecting electrically to the gate lines Fig 9-14.
Regarding claim 10, Lim discloses wherein the gate structure extends in a first direction, and the isolation insulating structure extends in a second direction intersecting the first direction Fig 14.
Regarding claim 11, Lim discloses wherein the isolation insulating structure includes dummy contact structures arranged in the second direction Fig 14.
Regarding claim 13, Lee discloses all the limitations but silent on the arraignment of the isolation structure. Whereas Lim discloses a semiconductor device comprising: a gate structure ¶0054 including gate lines and insulating layers that are alternately stacked Fig 14; a channel structure Fig 14, CCS¶0057 extending through the gate structure Fig 14; a dummy channel structure ¶0062 extending through the dummy gate structure Fig 14; and an isolation insulating structure Fig 14, TIP and Fig 14, 330 including horizontal portions stacked between the gate structure Fig 14 and vertical portions extending through the horizontal portions Fig 14. Lee and Lim are analogous art because they are directed to vertical memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lee because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the Lee’s device and incorporate the teachings of Lim to improve device isolation.
Regarding claim 14, Lee in view of Lim discloses wherein the dummy contact plugs are located on the horizontal portions, and the vertical portions surround sidewalls of the dummy contact plugs ¶0065 Fig 5A, 184d.
Claims 6, 9 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US Publication no. 2019/0043880) in view of Lim et al (US Publication No. 2021/0005629) and in further view of Kaminaga et al (US Publication No. 2021/0313281).
Regarding claim 6, Lee and Lim discloses all the limitations but silent on the chip device arrangement. Whereas Kaminaga discloses wherein in a memory block, the dummy gate structure and the isolation insulating structure are located in a block edge region, and the gate structure is located in a block center region ¶0194-0198 Fig 24B-25. Lee and Kaminaga are analogous art because they are directed to vertical memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lee because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify Lee’s device and incorporate the teachings of Kaminaga to improve device integration and performance.
Regarding claim 9, Lee and Lim discloses all the limitations but silent on the chip guard structure. Whereas Kaminaga discloses a chip guard structure Fig 1A-4B, 400, wherein the dummy gate structure is located between the chip guard structure and the isolation insulating structure Fig 1B-4B. Lee and Kaminaga are analogous art because they are directed to vertical memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lee because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify Lee’s device and incorporate the teachings of Kaminaga to improve device isolation and device protection.
Regarding claim 15, Kaminaga discloses a chip guard structure extending through the dummy gate structure Fig 1B-4B.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US Publication no. 2019/0043880) in view of Lim et al (US Publication No. 2021/0005629) and in further view of Kanamori et al (US Publication No. 2021/0118902).
Regarding claim 8, Lee and Lim discloses all the limitations but silent on spacer/liner. Whereas Kanamori discloses insulating spacers Fig 34, 590 surrounding sidewalls of the contact plugs Fig 34, 600. Lee and Kanamori are analogous art because they are directed to vertical memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lee because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify Lee’s device and incorporate the teachings of Kanamori to improve device insulation.
Conclusion
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/CHRISTINE A ENAD/Primary Examiner, Art Unit 2811