DETAILED ACTION
This office action is in response to amendment filed 7/1/2026.
Claims 21-31 are pending. Claims 1-20 have been canceled. Claims 21-31 are new.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 21-27 and 29-31 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Raheel et al. US 2024/0079331 (Raheel).
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In re claim 21, Raheel discloses (e.g. FIGs. 1-4) a semiconductor structure comprising:
a top interconnect 220,230 located on top of a stacked field-effect-transistor (FET) (see FIG. 2, ¶ 113);
a bottom interconnect 103,105,110 located on the bottom of the stack FET,
wherein the stacked FET comprises:
a first top source/drain SD2 (middle SD2 in FIG. 2 or SD2 in FIG. 4) and a second top source/drain (left SD2 in FIG. 2);
a first bottom source/drain SD1 (middle SD1 in FIG. 2 or SD1 in FIG. 4) and a second bottom source/drain (another SD1);
a first connecting via AV3 +180 that connects to the first bottom source/drain (middle SD1 in FIG. 2 or SD1 in FIG. 4) to the top interconnect 220,230, wherein the first connecting via AV3+180 includes a lateral extension 180 that directly connects to a bottom surface of the first bottom source/drain (middle SD1 in FIG. 2 or SD1 in FIG. 4);
a top contact 280+AV2+210 that is directly connected to a top surface of the first top source/drain (middle SD2 in FIG. 2 or SD2 in FIG. 4), wherein the top contact 280+AV2+210 has a lateral extension 210 that overlaps with the second top source/drain (left SD2 in FIG. 2) and overlaps with the second bottom source/drain (left SD1 in FIG. 2).
In re claim 22, Raheel discloses (e.g. FIGs. 2-4) wherein the top interconnect 220,230 includes a connecting via 220 that is connected to the lateral extension 210 of the top contact 280+AV2+210.
In re claim 23, Raheel discloses (e.g. FIG. 2 see below) wherein the connecting via 220 of the top interconnect 220,230 overlaps with the second top source/drain (left SD2 in FIG. 2) (overlap along the direction that intersect the connecting via and the second top source/drain as indicated by the dash line in FIG. 2 annotated below).
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In re claim 24, Raheel discloses (e.g. FIGs. 2-4) further comprising:
a second connecting via 190,290,VCT,AV4 that connects (indirectly connects through FET or other connection layers) the second top source/drain (left SD2) to the bottom interconnect 103,105,110.
In re claim 25, Raheel discloses (e.g. FIG. 2) wherein the second connecting via 190,290,VCT,AV4 has a vertical section and a lateral section. Each of the vias 190,290,VCT,AV4 is a 3D structure having a vertical section and a lateral section.
In re claim 26, Raheel discloses (e.g. FIG. 2) wherein the vertical section of the second connecting via 190,290 (any vertical section of 190,290) extends between the first bottom source/drain (middle SD1 in FIG. 2) and the second bottom source/drain (left SD1 in FIG. 2).
In re claim 27, Raheel discloses (e.g. FIG. 4) wherein the lateral section of second connecting via VCT,AV4 extends laterally through a bonding layer ILD4 (VCT,AV4 having a lateral extents in ILD4), wherein the bonding layer ILD4 is located between the second top source/drain (left SD2 in FIG. 2) and the second bottom source/drain (left SD1 in FIG. 2).
In re claim 29, Raheel discloses (e.g. FIG. 4) wherein the lateral extension 180 of the first connecting via AV3 +180 is comprised of a horizontal section and a vertical section (180 is 3D structure having a horizontal section and a vertical section, e.g. a lower horizontal section of 180 and an upper vertical section of 180, see FIG. 4 annotated below).
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In re claim 30, Raheel discloses (e.g. FIG. 4) wherein the horizontal section of the lateral extension 180 (e.g. lower horizontal section of 180) extends through a shallow trench isolation layer (upper portion of ILD 2).
In re claim 31, Raheel discloses (e.g. FIG. 4) wherein the vertical section of the lateral extension 180 (e.g. upper vertical section of 180) extends vertically from the horizontal section (lower horizontal vertical section of 180) to directly connect with the bottom surface of the first bottom source/drain SD1.
Claims 21-31 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lai et al. US 2022/0336325 A1 (Lai).
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In re claim 21, Lai discloses (e.g. FIG. 6B flipped upside as shown above) a semiconductor structure comprising:
a top interconnect (interconnect level including 652) located on top of a stacked field-effect-transistor (FET) (when device of FIG. 6B is flipped upside down);
a bottom interconnect (interconnect level including 666) located on the bottom of the stack FET (when device of FIG. 6B is flipped upside down),
wherein the stacked FET comprises:
a first top source/drain and a second top source/drain (see annotated in FIG. 6 above);
a first bottom source/drain and a second bottom source/drain (see annotated in FIG. 6 above);
a first connecting via 660+654 that connects to the first bottom source/drain to the top interconnect 652, wherein the first connecting via 660+654 includes a lateral extension 660 that directly connects to a bottom surface of the first bottom source/drain;
a top contact (see annotated in FIG. 6 above) that is directly connected to a top surface of the first top source/drain, wherein the top contact has a lateral extension that overlaps with the second top source/drain (in a region that is behind the view shown in the page) and overlaps with the second bottom source/drain.
In re claim 22, Lai discloses (e.g. see FIG. 6B above) wherein the top interconnect includes a connecting via (via above 1st top SD) that is connected to the lateral extension of the top contact.
In re claim 23, Lai discloses (e.g. see FIG. 6B above) wherein the connecting via of the top interconnect overlaps with the second top source/drain (overlap along the direction that intersect the connecting via and the second top source/drain as indicated by the dash line in FIG. 6B annotated above).
In re claim 24, Lai discloses (e.g. see FIG. 6B above) further comprising:
a second connecting via 658+662 that connects the second top source/drain to the bottom interconnect (see annotated FIG. 6B above).
In re claim 25, Lai discloses (e.g. see annotated FIG. 6B above) wherein the second connecting via has a vertical section 662 and a lateral section 658.
In re claim 26, Lai discloses (e.g. see annotated FIG. 6B above) wherein the vertical section 662 of the second connecting via extends between the first bottom source/drain and the second bottom source/drain (662 extends between ends of the bottom source/drains as shown in annotated FIG. 6B above).
In re claim 27, Lai discloses (e.g. see annotated FIG. 6B above) wherein the lateral section 658 of second connecting via extends laterally through a bonding layer (no specific bonding layer claimed that would distinguish over a layer between the top and bottom s/d, e.g. 603 shown in FIG. 6A or other surrounding dielectric material), wherein the bonding layer is located between the second top source/drain and the second bottom source/drain.
In re claim 28, Lai discloses (e.g. see annotated FIG. 6B above) wherein the lateral section 658 of second connecting via directly contacts a bottom surface of the second top source/drain, wherein the lateral section 658 of second connecting via overlaps with the second bottom source/drain.
In re claim 29, Lai discloses (e.g. see annotated FIG. 6B above) wherein the lateral extension 660 of the first connecting via is comprised of a horizontal section and a vertical section (660 is 3D structure having a horizontal section and a vertical section, e.g. a lower horizontal section of 660 and an upper vertical section of 660, see FIG. 6B annotated above).
In re claim 30, Lai discloses (e.g. see annotated FIG. 6B above) wherein the horizontal section of the lateral extension 660 extends through a shallow trench isolation layer (not shown, dielectric layer laterally surrounding 660).
In re claim 31, Lai discloses (e.g. see annotated FIG. 6B above) wherein the vertical section of the lateral extension 660 extends vertically from the horizontal section to directly connect with the bottom surface of the first bottom source/drain.
Response to Arguments
Applicant’s arguments with respect to claim(s) 21-31 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU CHEN whose telephone number is (571)270-7881. The examiner can normally be reached Monday-Friday: 9AM-5PM ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, WILLIAM KRAIG can be reached on 5712728660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YU CHEN/Primary Examiner, Art Unit 2896
YU CHEN
Examiner
Art Unit 2896
Prosecution Insights