DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election without traverse of Invention I, (claims 1-14), in the reply filed on
03/09/2026 is acknowledged. Claims 1-20 are pending.
Claim Objections
Claim 7 is objected to because of the following informalities: “…wherein when the chip
assembly rests on …”. It should be read “…wherein the chip assembly rests on…”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 7 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-
AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Re: claim 7, it recites the limitation “…wherein when the chip assembly rests on a horizontal surface with a chip facing away from the surface, the planar surface of the wirebond wire is substantially parallel to the horizontal surface…” is not explained. The limitation has an antecedent issue of “a chip, the surface and the planar surface”. Therefore, it is indefinite. For the examination purpose and according to claim 1, the limitation “…wherein when the chip assembly rests on a horizontal surface with a chip facing away from the surface, the planar surface of the wirebond wire is substantially parallel to the horizontal surface…” is interpreted as “…wherein when the chip assembly rests on a horizontal surface with the chip facing away from the horizontal surface, the flat-pressed surface of the wirebond wire is substantially parallel to the horizontal surface…”.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7 and 12-14 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Launay (US 20190303738 A1, hereinafter Launay) in view of Yamamoto (US 4961105 A, hereinafter Yamamoto).
Re: Independent Claim 1, Launay discloses a chip assembly (Fig. 20), comprising:
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Launay’s Figure 20-Annotated.
a carrier (S carrier [0081], Fig. 20) with a cavity (Cav2 cavity central portion [0128], Fig. 20) and at least one carrier contact (P1, P2, P3, P5, P6, P7, PL1, PL2 external electrical contact [0081, 0085], Fig. 20);
a chip (MP chip [0081], Fig. 20) arranged in the cavity (Cav2, Fig. 20) and having at least one chip contact (connection points in MP [0081], Fig. 20-Annotated); and
at least one wirebond wire (Fil1, Fil2, Fil3, Fil4, Fil5 wires from MP chip [0081], Fig. 20) which electrically conductively connects (Fil1, Fil2, Fil3, Fil4, Fil5 wires from MP chip to connect P1, P2, P3, P5, P6, P7, [0081], Fig. 20) the at least one chip contact (connection points in MP, Fig. 20) to the at least one carrier contact (P1, P2, P3, P5, P6, P7, Fig. 20),
Launay does not expressly disclose wherein the wirebond wire is flat-pressed in at least one subregion.
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Yamamoto’s Figure 3-Annotated.
However, in the same semiconductor device field of endeavor, Yamamoto discloses a wirebond wire (4 bonding wires in Col. 4, line 20, Fig. 3) is flat-pressed in at least one subregion (2subRegion a flat portion in Fig. 3-Annotated).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to made the Launay’s wirebond wire flat-pressed in at least one subregion according to Yamamoto’s device to make the device thinner (Col. 1, lines 19-20, Yamamoto).
Re: Claim 2, Launay modified by Yamamoto discloses the chip assembly as claimed in claim 1, wherein the wirebond wire (Fil1, Fil2, Fil3, Fil4, Fil5 Launay) has a round or polygonal (Fil1, Fil2, Fil3, Fil4, Fil5 are wires with round shape, Launay) cross-section outside the at least one subregion (Yamamoto applied to Launay).
Re: Claim 3, Launay modified by Yamamoto discloses the chip assembly as claimed in claim 1, in wherein the wirebond wire (Fil1, Fil2, Fil3, Fil4, Fil5 Launay) is flatter (Yamamoto applied to Launay) in the at least one subregion (Yamamoto’s 1region applied to Launay) than in another region of the wirebond wire (Fil1, Fil2, Fil3, Fil4, Fil5 Launay).
Re: Claim 4, Launay modified by Yamamoto discloses the chip assembly as claimed in claim 1,
Launay modified by Yamamoto does not expressly disclose wherein the at least one flat-pressed subregion has a first subregion, which in a plan view of the chip assembly lies within a surface region of the chip contact, and/or a second subregion, which in plan view lies within a surface region of the carrier contact.
However, in the same semiconductor device field of endeavor, Yamamoto discloses wherein the at least one flat-pressed subregion has a first subregion (1subRegion a flat portion in Fig. 3-Annotated), which in a plan view of the chip assembly lies within a surface region of the chip contact (top layer of semiconductor pellet 1 in Col. 4, lines 4-5, Fig. 3-Annotated), and/or a second subregion (2subRegion a flat portion in Fig. 3-Annotated), which in plan view lies within a surface region of the carrier contact (2y metallic pattern in Col. 4, lines 4-5, Fig. 3-Annotated)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to made the Launay’s wirebond wire having at least one flat-pressed subregion has a first subregion, which in a plan view of the chip assembly lies within a surface region of the chip contact, and/or a second subregion, which in plan view lies within a surface region of the carrier contact according to Yamamoto’s device to make the device thinner (Col. 1, lines 19-20, Yamamoto).
Re: Claim 5, Launay modified by Yamamoto discloses the chip assembly as claimed in claim 1, wherein the wirebond wire (Fil1, Fil2, Fil3, Fil4, Fil5 Launay) has a planar surface in the at least one subregion (Yamamoto’s 1region applied to Launay).
Re: Claim 6, Launay modified by Yamamoto discloses the chip assembly as claimed in claim 1, further comprising: an antenna (antenna [0085], Fig. 20 Launay) mounted on a surface of the carrier (S carrier [0081], Fig. 20 Launay), wherein the carrier contact (P1, P2, P3, P5, P6, P7, PL2, PL1 external electrical contact [0081, 0085], Fig. 20 Launay) is electrically conductively (all connections are electrically connected Launay) connected to the antenna (antenna [0085], Fig. 20 Launay).
Re: Claim 7, Launay modified by Yamamoto discloses the chip assembly as claimed in claim 1, in wherein when the chip assembly rests on a horizontal surface with the chip facing away (Fig. 20 Launay) from the horizontal surface, the flat-pressed surface of the wirebond wire (Fil1, Fil2, Fil3, Fil4, Fil5 Launay) is substantially parallel (Yamamoto’s 1region, as showed in Fig.3 and applied to Launay) to the horizontal surface.
Re: Claim 12, Launay modified by Yamamoto discloses the chip assembly as claimed in claim 1, wherein the chip is a security chip (an identity card or a passport in [0003] Launay).
Re: Claim 13, Launay modified by Yamamoto discloses a document structure, comprising: a first document layer (a layer as part of laminated structure in [0026] Launay); a second document layer (a layer as part of laminated structure in [0026] Launay); and a chip assembly as claimed in claim 1 between (the inlay is laminated between at least two other layers forming at least part of the body in [0026] Launay) the first document layer and the second document layer.
Re: Independent Claim 14, Launay discloses a method for forming a chip assembly (Fig. 20), the method comprising:
forming a cavity (Cav2 cavity central portion [0128], Fig. 20) in a carrier (S carrier [0081], Fig. 20);
applying a carrier contact (P1, P2, P3, P5, P6, P7, PL1, PL2 external electrical contact [0081, 0085], Fig. 20) to the carrier (S carrier [0081], Fig. 20);
arranging a chip (MP chip [0081], Fig. 20) having at least one chip contact (connection points in MP [0081], Fig. 20) in the cavity (Cav2 cavity central portion [0128], Fig. 20);
electrically conductively connecting the chip contact (connection points in MP [0081], Fig. 20) and the carrier contact (P1, P2, P3, P5, P6, P7, PL1, PL2, Fig. 20) using a wirebond wire (Fil1, Fil2, Fil3, Fil4, Fil5 wires from MP chip [0081], Fig. 20).
Launay does not expressly disclose flat-pressing the wirebond wire in at least one subregion.
However, in the same semiconductor device manufacturing field of endeavor, Yamamoto discloses flat-pressing the wirebond wire (4 bonding wires in Col. 4, line 20, Fig. 3) in at least one subregion (1Region a flat portion in Fig. 3-Annotated).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to made the Launay’s wirebond wire flat-pressing in at least one subregion according to Yamamoto’s method to make the device thinner (Col. 1, lines 19-20, Yamamoto).
Claim(s) 8-10 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Launay in view of Yamamoto and further in view of Ayala (US 6517005 B1, hereinafter Ayala).
Re: Claim 8, Launay modified by Yamamoto discloses the chip assembly as claimed in claim 1, wherein the chip (MP chip [0081], Fig. 20 Launay) has a plurality of edges forming a polygon (Fig. 20 Launay), and
Launay modified by Yamamoto does not expressly disclose wherein a single chip contact of the at least one chip contact extends along at least two edges.
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Ayala’s Figure 2-Annotated.
However, in the same semiconductor device manufacturing field of endeavor, Ayala discloses wherein a single chip contact (27 connection in L-shape, Col. 4 lines 4-5, Fig. 2) of the at least one chip contact (26, 27 Col. 4 lines 4-5, Fig. 2) extends along at least two edges (edges of 22 Fig. 2-Annotated).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Ayala’s feature wherein a single chip contact of the at least one chip contact extends along at least two edges to the combination of Launay and Yamamoto to provide a device which best resolves the different constraints of sizing, manufacturing precision, mechanical strength, and more generally reliability, cost and efficiency in manufacturing the card (Col. 1 lines 55-59, Ayala).
Re: Claim 9, Launay modified by Yamamoto and Ayala discloses the chip assembly as claimed in claim 8, wherein the wirebond wire (Fil1, Fil2, Fil3, Fil4, Fil5 Launay) contacts the single chip contact (Ayala’s 27 applied to Launay) across at least one of the at least two edges (edges of 22 Fig. 2-Annotated, Ayala).
Re: Claim 10, Launay modified by Yamamoto discloses the chip assembly as claimed in claim 1,
Launay modified by Yamamoto does not expressly disclose wherein the at least one chip contact is L-shaped.
However, in the same semiconductor device manufacturing field of endeavor, Ayala discloses wherein the at least one chip contact (27 connection in L-shape, Col. 4 lines 4-5, Fig. 2) is L-shaped.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Ayala’s feature wherein the at least one chip contact is L-shaped to the combination of Launay and Yamamoto to provide a device which best resolves the different constraints of sizing, manufacturing precision, mechanical strength, and more generally reliability, cost and efficiency in manufacturing the card (Col. 1 lines 55-59, Ayala).
Claim(s) 11 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Launay in view of Yamamoto and further in view of Nitta (US 20240028861 A1, hereinafter Nitta).
Re: Claim 11, Launay modified by Yamamoto discloses the chip assembly as claimed in claim 1, Launay modified by Yamamoto does not expressly disclose wherein the chip assembly has a
maximum thickness (H3) of 80 µm.
However, in the same semiconductor device field of endeavor, Nitta discloses wherein the
chip assembly (Fig. 2) has a maximum thickness (H3) of 80 µm (a substrate of 10 µm and an antenna of 20 µm, wherein the complete assembly is less than 80 µm [0035, 0041]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Nitta’s feature wherein the chip assembly has a maximum thickness (H3) of 80 µm to the combination of Launay and Yamamoto for reducing the manufacturing cost ([0041], Nitta).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Finn (US 11755873 B1) teaches “RFID ENABLED METAL TRANSACTION CARDS”. This document is related to a metal containing transaction cards or smartcards (SC) having a slit (S) formed in a metal layer (ML) or metal card body (MCB) which extends from a perimeter edge of the card body to a transponder chip module (TCM), wherein the path of the slit (S) extends to an area underneath a module antenna (MA) of the TCM. The slit (S) does not reach a module opening (MO) for the transponder chip module (TCM). The slit enters the area of the module antenna (MA) overlapping its windings or tracks and follows the form and path of the module antenna (MA). In some embodiments, the module opening (MO) may be omitted. The shape of the module opening (MO) may be other than rectangular, and it may have at least two parallel sides.
Glaris (US 20240039142 A1) teaches “METHOD FOR MANUFACTURING CHIP CARD MODULES AND BAND OF FLEXIBLE MATERIAL SUPPORTING SUCH MODULES”. This document is related to a method for the manufacture of a chip card module in which a polymer material including conductive particles is deposited in two connection wells or on two conductive pads formed in a conductive sheet positioned on the back face of the module. This polymer material forms, after deposition, an excess thickness on the back face which comes, during the insetting of the module, into contact with the ends of an antenna. Between the manufacture of the modules and their insetting, the modules are positioned on a strip which can be rolled up on itself for the purpose of its storage.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANDRA M RODRIGUEZ VILLANUEVA whose telephone number is (571)272-1936. The examiner can normally be reached Monday to Friday 8:00am-5:00pm (EST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571) 272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SANDRA MILENA RODRIGUEZ VILLANUEVA/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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