DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on 08/06/2026 has been entered. Applicant's amendment to the Claims
have overcome the claim objection and the 112(b) rejection previously set forth in the Non-Final Office Action dated on 04/28/2026. Claims 15-20 are withdrawn by consideration. Claims 1-20 are pending.
Response to Arguments
Applicant’s arguments "Applicant Arguments/Remarks Made in an Amendment" with the
"Amendment/Req. Reconsideration-After Non-Final Reject" filed on 08/06/2026, have been fully considered.
The Applicant’s arguments describe that “Yamamoto's bonding wires are conventional and are never flat-pressed… …Yamamoto's bonding wires 4 are ordinary looped wire bonds that are encapsulated in resin, not a wire "flat-pressed in at least one subregion"… …The "flat" features identified in the rejection are not part of any wirebond wire. The Office Action maps the alleged "flat-pressed subregion" to element "2" (Yamamoto's circuit board) … …Yamamoto reduces thickness by a different mechanism, unrelated to the wire. Yamamoto achieves a thinner card by (i) forming the circuit board 2 of a thin polyimide film accommodating the pellet in a recess 9…". However, the Applicant’s arguments are not persuasive because the Yamamoto’s device (US 4961105 A) describes that bonding wires 4 having a flat portion indicated in the office action, as “2subRegion” in Figure 3-Annotated. The office action does not map "flat-pressed subregion" to element "2". In Figure 3-Annotated two subregions of the bond wire 4 are showed the 1subRegion and the 2subRegion. In addition, Yamamoto’s device includes the bonding wire 4 with a flat portion, then, this element as part of the device contribute to the reduction of thickness of the device in an area outside of the top surface of the semiconductor pellet 1 (Col 4, line 19, Yamamoto).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 7 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-
AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Re: claim 7, recites the limitation “the chip assembly rests on a horizontal surface with the chip facing away from the horizontal surface” at lines 2-3. It is unclear as to what the horizontal surface is part of. Further, it is unclear how the chip assembly rests on a horizontal surface of some element, but does not face said horizontal surface.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7 and 12-14 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Launay (US 20190303738 A1, hereinafter Launay, of the record) in view of Yamamoto (US 4961105 A, hereinafter Yamamoto, of the record).
Re: Independent Claim 1, Launay discloses a chip assembly (Fig. 20), comprising:
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Launay’s Figure 20-Annotated.
a carrier (S carrier [0081], Fig. 20) with a cavity (Cav2 cavity central portion [0128], Fig. 20) and at least one carrier contact (P1, P2, P3, P5, P6, P7, PL1, PL2 external electrical contact [0081, 0085], Fig. 20);
a chip (MP chip [0081], Fig. 20) arranged in the cavity (Cav2, Fig. 20) and having at least one chip contact (connection points in MP [0081], Fig. 20-Annotated); and
at least one wirebond wire (Fil1, Fil2, Fil3, Fil4, Fil5 wires from MP chip [0081], Fig. 20) which electrically conductively connects (Fil1, Fil2, Fil3, Fil4, Fil5 wires from MP chip to connect P1, P2, P3, P5, P6, P7, [0081], Fig. 20) the at least one chip contact (connection points in MP, Fig. 20) to the at least one carrier contact (P1, P2, P3, P5, P6, P7, Fig. 20),
Launay does not expressly disclose wherein the wirebond wire is flat-pressed in at least one subregion.
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Yamamoto’s Figure 3-Annotated.
However, in the same semiconductor device field of endeavor, Yamamoto discloses a wirebond wire (4 bonding wires in Col. 4, line 20, Fig. 3) is flat-pressed in at least one subregion (2subRegion a flat portion of bond wire 4, in Fig. 3-Annotated).
It would have been obvious to one of ordinary skill in the art, absent unexpected results, before the effective filing date of the claimed invention to made the Launay’s wirebond wire flat-pressed in at least one subregion according to Yamamoto’s device in order to have the predictable result of using a wirebonding technique that is known to make reliable electrical and structural connections. Further, wedge and ball bonds are known in the art as wirebond terminations.
Re: Claim 2, Launay modified by Yamamoto discloses the chip assembly as claimed in claim 1, wherein the wirebond wire (Fil1, Fil2, Fil3, Fil4, Fil5 Launay) has a round or polygonal (Fil1, Fil2, Fil3, Fil4, Fil5 are wires with round shape, Launay) cross-section outside the at least one subregion (Yamamoto applied to Launay).
Re: Claim 3, Launay modified by Yamamoto discloses the chip assembly as claimed in claim 1, in wherein the wirebond wire (Fil1, Fil2, Fil3, Fil4, Fil5 Launay) is flatter (Yamamoto applied to Launay) in the at least one subregion (Yamamoto’s 1region applied to Launay) than in another region of the wirebond wire (Fil1, Fil2, Fil3, Fil4, Fil5 Launay).
Re: Claim 4, Launay modified by Yamamoto discloses the chip assembly as claimed in claim 1,
Launay modified by Yamamoto does not expressly disclose wherein the at least one flat-pressed subregion has a first subregion, which in a plan view of the chip assembly lies within a surface region of the chip contact, and/or a second subregion, which in plan view lies within a surface region of the carrier contact.
However, in the same semiconductor device field of endeavor, Yamamoto discloses wherein the at least one flat-pressed subregion has a first subregion (1subRegion a flat portion in Fig. 3-Annotated), which in a plan view of the chip assembly lies within a surface region of the chip contact (top layer of semiconductor pellet 1 in Col. 4, lines 4-5, Fig. 3-Annotated), and/or a second subregion (2subRegion a flat portion in Fig. 3-Annotated), which in plan view lies within a surface region of the carrier contact (2y metallic pattern in Col. 4, lines 4-5, Fig. 3-Annotated)).
It would have been obvious to one of ordinary skill in the art, absent unexpected results, before the effective filing date of the claimed invention to made the Launay’s wirebond wire having at least one flat-pressed subregion has a first subregion, which in a plan view of the chip assembly lies within a surface region of the chip contact, and/or a second subregion, which in plan view lies within a surface region of the carrier contact according to Yamamoto’s device in order to have the predictable result of making the device thinner (Col. 1, lines 19-20, Yamamoto).
Re: Claim 5, Launay modified by Yamamoto discloses the chip assembly as claimed in claim 1, wherein the wirebond wire (Fil1, Fil2, Fil3, Fil4, Fil5 Launay) has a planar surface in the at least one subregion (Yamamoto’s 1region applied to Launay).
Re: Claim 6, Launay modified by Yamamoto discloses the chip assembly as claimed in claim 1, further comprising: an antenna (antenna [0085], Fig. 20 Launay) mounted on a surface of the carrier (S carrier [0081], Fig. 20 Launay), wherein the carrier contact (P1, P2, P3, P5, P6, P7, PL2, PL1 external electrical contact [0081, 0085], Fig. 20 Launay) is electrically conductively (all connections are electrically connected Launay) connected to the antenna (antenna [0085], Fig. 20 Launay).
Re: Claim 7, Launay modified by Yamamoto discloses the chip assembly as claimed in claim 1, wherein the chip assembly rests on a horizontal surface with the chip facing away (Fig. 20 Launay) from the horizontal surface, the flat-pressed surface of the wirebond wire (Fil1, Fil2, Fil3, Fil4, Fil5 Launay) is substantially parallel (Yamamoto’s 1region, as showed in Fig.3 and applied to Launay) to the horizontal surface.
Re: Claim 12, Launay modified by Yamamoto discloses the chip assembly as claimed in claim 1, wherein the chip is a security chip (an identity card or a passport in [0003] Launay).
Re: Claim 13, Launay modified by Yamamoto discloses a document structure, comprising: a first document layer (a layer as part of laminated structure in [0026] Launay); a second document layer (a layer as part of laminated structure in [0026] Launay); and a chip assembly as claimed in claim 1 between (the inlay is laminated between at least two other layers forming at least part of the body in [0026] Launay) the first document layer and the second document layer.
Re: Independent Claim 14, Launay discloses a method for forming a chip assembly (Fig. 20), the method comprising:
forming a cavity (Cav2 cavity central portion [0128], Fig. 20) in a carrier (S carrier [0081], Fig. 20);
applying a carrier contact (P1, P2, P3, P5, P6, P7, PL1, PL2 external electrical contact [0081, 0085], Fig. 20) to the carrier (S carrier [0081], Fig. 20);
arranging a chip (MP chip [0081], Fig. 20) having at least one chip contact (connection points in MP [0081], Fig. 20) in the cavity (Cav2 cavity central portion [0128], Fig. 20);
electrically conductively connecting the chip contact (connection points in MP [0081], Fig. 20) and the carrier contact (P1, P2, P3, P5, P6, P7, PL1, PL2, Fig. 20) using a wirebond wire (Fil1, Fil2, Fil3, Fil4, Fil5 wires from MP chip [0081], Fig. 20).
Launay does not expressly disclose flat-pressing the wirebond wire in at least one subregion.
However, in the same semiconductor device manufacturing field of endeavor, Yamamoto discloses flat-pressing the wirebond wire (4 bonding wires in Col. 4, line 20, Fig. 3) in at least one subregion (1Region a flat portion in Fig. 3-Annotated).
It would have been obvious to one of ordinary skill in the art, absent unexpected results, before the effective filing date of the claimed invention to make the Launay’s wirebond wire flat-pressing in at least one subregion according to Yamamoto’s method in order to have the predictable result of making the device thinner (Col. 1, lines 19-20, Yamamoto).
Claim(s) 8-10 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Launay in view of Yamamoto and further in view of Ayala (US 6517005 B1, hereinafter Ayala, of the record).
Re: Claim 8, Launay modified by Yamamoto discloses the chip assembly as claimed in claim 1, wherein the chip (MP chip [0081], Fig. 20 Launay) has a plurality of edges forming a polygon (Fig. 20 Launay), and
Launay modified by Yamamoto does not expressly disclose wherein a single chip contact of the at least one chip contact extends along at least two edges.
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Ayala’s Figure 2-Annotated.
However, in the same semiconductor device manufacturing field of endeavor, Ayala discloses wherein a single chip contact (27 connection in L-shape, Col. 4 lines 4-5, Fig. 2) of the at least one chip contact (26, 27 Col. 4 lines 4-5, Fig. 2) extends along at least two edges (edges of 22 Fig. 2-Annotated).
It would have been obvious to one of ordinary skill in the art, absent unexpected results, before the effective filing date of the claimed invention to include the Ayala’s feature wherein a single chip contact of the at least one chip contact extends along at least two edges to the combination of Launay and Yamamoto in order to have the predictable result of providing a device which best resolves the different constraints of sizing, manufacturing precision, mechanical strength, and more generally reliability, cost and efficiency in manufacturing the card (Col. 1 lines 55-59, Ayala).
Re: Claim 9, Launay modified by Yamamoto and Ayala discloses the chip assembly as claimed in claim 8, wherein the wirebond wire (Fil1, Fil2, Fil3, Fil4, Fil5 Launay) contacts the single chip contact (Ayala’s 27 applied to Launay) across at least one of the at least two edges (edges of 22 Fig. 2-Annotated, Ayala).
Re: Claim 10, Launay modified by Yamamoto discloses the chip assembly as claimed in claim 1,
Launay modified by Yamamoto does not expressly disclose wherein the at least one chip contact is L-shaped.
However, in the same semiconductor device manufacturing field of endeavor, Ayala discloses wherein the at least one chip contact (27 connection in L-shape, Col. 4 lines 4-5, Fig. 2) is L-shaped.
It would have been obvious to one of ordinary skill in the art, absent unexpected results, before the effective filing date of the claimed invention to include the Ayala’s feature wherein the at least one chip contact is L-shaped to the combination of Launay and Yamamoto in order to have the predictable result of providing a device which best resolves the different constraints of sizing, manufacturing precision, mechanical strength, and more generally reliability, cost and efficiency in manufacturing the card (Col. 1 lines 55-59, Ayala).
Claim(s) 11 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Launay in view of Yamamoto and further in view of Nitta (US 20240028861 A1, hereinafter Nitta, of the record).
Re: Claim 11, Launay modified by Yamamoto discloses the chip assembly as claimed in claim 1, Launay modified by Yamamoto does not expressly disclose wherein the chip assembly has a
maximum thickness (H3) of 80 µm.
However, in the same semiconductor device field of endeavor, Nitta discloses wherein the
chip assembly (Fig. 2) has a maximum thickness (H3) of 80 µm (a substrate of 10 µm and an antenna of 20 µm, wherein the complete assembly is less than 80 µm [0035, 0041]).
It would have been obvious to one of ordinary skill in the art, absent unexpected results, before the effective filing date of the claimed invention to include the Nitta’s feature wherein the chip assembly has a maximum thickness (H3) of 80 µm to the combination of Launay and Yamamoto in order to have the predictable result of reducing the manufacturing cost ([0041], Nitta).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANDRA M RODRIGUEZ VILLANUEVA whose telephone number is (571)272-1936. The examiner can normally be reached Monday to Friday 8:00am-5:00pm (EST).
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/SANDRA MILENA RODRIGUEZ VILLANUEVA/
Examiner, Art Unit 2898
/JESSE Y MIYOSHI/
Primary Examiner, Art Unit 2898
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