DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted has been considered by the examiner.
Claim Objections
The claim(s) is/are objected to because of the following informalities:
Claim 8: it appears that “the first selection line” and “the second selection line” in line(s) 6-7 was meant to be -- a first selection line -- and -- a second selection line --; “the word line voltage” in line(s) 10 was meant to be -- a word line voltage --; “the first different region” and “the second different region” in line(s) 14 and 16 was meant to be -- the first region -- and -- the second region -- and will be construed as such for purposes of examination.
Claim 11: it appears that “payers” in line(s) 3 was meant to be -- layers --; “the layer for a drain side selection line” in line(s) 7 was meant to be -- the layer for the drain side selection line -- and will be construed as such for purposes of examination.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-9, 12-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Maejima (US 2014/0254270).
Regarding claim 1, Maejima discloses a non-volatile storage apparatus, comprising:
a plurality of non-volatile memory cells (“blocks BLK (BLK0 to BLK3) which are each a grouping of nonvolatile memory cells” para 0036) positioned in different regions (i.e. positioned in different NAND string regions 17; fig. 2) of non-volatile memory cells (memory cell transistors MT (MT0 to MT7); fig. 2);
a first word line (any of word line WL0-WL7, i.e. WL0; fig. 2) connected to each non-volatile memory cell (“control gates of the memory cell transistors MT0 to MT7 in the same block BLK0 are commonly connected to word lines WL0 to WL7” para 0047) of the plurality of non-volatile memory cells positioned in different regions (WL0 connected to each MT0 in different NAND string regions 17; fig. 2);
a plurality of separate and independently controlled (i.e. via row decoders 11-0 to 11-3; fig. 1, 3) selection lines (“selection gate lines SGD and SGS are independent for each of memory groups GP0 to GP3” para 0048) connected to the non-volatile memory cells (MT0-MT7), each region of the different regions (i.e. each NAND string regions 17) is connected to a different selection line (different selection line(s) SGD0-SGD3 and SGS0-SGS3; fig. 2) of the plurality of separate and independently controlled selection lines (i.e. NAND string region(s) 17 of GP0 is connected to SGD0 and SGS0, NAND string region(s) 17 of GP1 is connected to SGD1 and SGS0, …; fig. 2); and
a control circuit (12; fig. 3) connected to the plurality of separate and independently controlled selection lines (SGD0-SGD3 and SGS0-SGS3; fig. 3) and to the first word line (WL0; fig. 3), the control circuit (12) is configured to apply a voltage (during a read operation, apply a voltage VSLCV; fig. 15 para 0104) to the first word line (WL0, i.e. selected word line; para 0165) and sequentially sense data (“read out in order [i.e. sequentially] from the pages PG0 to PG11” fig. 14, 15, para 0165) from non-volatile memory cells (“sense amplifier 13 senses and amplifies the data read out from the memory cells when reading out the data” para 0039) positioned in different regions (NAND string regions 17) without recharging the voltage (i.e. VSLCV remains constant; fig. 14) applied to the first word line (WL0).
Regarding claim 2, Maejima discloses the non-volatile storage, further comprising: a bit line (any bit line BL0-BLn; fig. 2) connected to each non-volatile memory cell of the plurality of non-volatile memory cells positioned in different regions, the control circuit is configured to sequentially sense data (data is read out sequentially from page to page; para 0165) from the non-volatile memory cells positioned in different regions and connected to the bit line (fig. 11, 15) without recharging the voltage applied to the first word line (i.e. VSLCV applied to WL0 remains constant; fig. 15).
Regarding claim 3, Maejima discloses the non-volatile storage, wherein: the control circuit is configured to recharge the bit line multiple times (i.e. charged during first and second read out; para 0134) while sensing data from non-volatile memory cells positioned in different regions without recharging the voltage applied to the first word line (i.e. VSLCV applied to WL0 remains constant; fig. 15).
Regarding claim 4, Maejima discloses the non-volatile storage, wherein: the control circuit is configured to apply the voltage to the first word line and sequentially sense data from non-volatile memory cells positioned in different regions while continuing to apply the voltage to the first word line (i.e. VSLCV applied to WL0 remains constant; fig. 15).
Regarding claim 5, Maejima discloses the non-volatile storage, wherein: the voltage applied to the first word line (VSLCV) is in a first range of voltages (a range of voltages generated by voltage generation circuit 15, i.e. VPGMH, VREADH, VPASS, and VSLCV; para 0097) associated with testing for a particular data state (VSLCV is applied in testing to verify for a data state having a threshold voltage; fig. 13 para 0143); and the control circuit is configured to sequentially sense data from non-volatile memory cells positioned in different regions while continuing to apply one or more voltages (i.e. VSLCV remains constant; fig. 14) to the first word line (WL0) that are in the first range of voltages (VPGMH, VREADH, VPASS, and VSLCV) associated with testing for the particular data state (fig. 13).
Regarding claim 6, Maejima discloses the non-volatile storage, wherein: the plurality of non-volatile memory cells are each on separate NAND strings (fig. 2); and the plurality of separate and independently controlled selection lines are drain side selection lines (para 0109) each connected to a subset of the NAND strings (each GP0-GP3 having a subset of NAND string 17 connected to respective SGD; fig. 2).
Regarding claim 7, Maejima discloses the non-volatile storage, wherein: the control circuit is configured to sequentially sense data from non-volatile memory cells positioned in different regions when a respective separate and independently controlled selection line is toggled on (i.e. switched on; fig. 3).
Regarding claim 8, Maejima discloses the non-volatile storage, wherein: the different regions of non-volatile memory cells include a first region of non-volatile memory cells (upper region separated by back gate transistor BT; fig. 2) and a second region of non-volatile memory cells (lower region separated by back gate transistor BT; fig. 2); the plurality of separate and independently controlled selection lines include a first region (first SGD region; fig. 2) and a second region (second SGS region; fig. 2); the first selection line (any of SGD0-SGD3; fig. 3) selects and enables (i.e. via the row decoder; fig. 3) memory operations for the first region (para 0067-0069); the second selection line (any of SGS0-SGS3; fig. 3) selects and enables (i.e. via the row decoder; fig. 3) memory operations for the second region (para 0071-0072); and the control circuit is configured to sequentially sense data from non-volatile memory cells positioned in different regions by, while continuing to apply the word line voltage to the first word line (i.e. VSLCV remains constant; fig. 14): first toggles on and then off (i.e. switched on/off during t0-t1, t1-t2, t2-t3…; fig. 15) the first selection line (i.e. SGD0) and subsequently toggles on and then off (i.e. switched on/off during t0-t1, t1-t2, t2-t3…; fig. 15) the second selection line (i.e. SGS1), senses data (i.e. via the sense amplifier) in the non-volatile memory cells in the first different region when the first selection line is toggled on and the second selection line is off (i.e. SGD0 is switched on while SGS1 is off during t0-t1; fig. 15), and senses data (i.e. via the sense amplifier) in the non-volatile memory cells in the second different regions when the second selection line is toggled on and the first selection line is off (i.e. SGS1 is switched on while SDG0 is off during t1-t2; fig. 15).
Regarding claim 9, Maejima discloses the non-volatile storage, wherein: the different regions of non-volatile memory cells are all in one block (fig. 2).
Regarding claim 12, Maejima discloses the non-volatile storage, wherein: the voltage applied to the first word line is a read reference voltage (fig. 4) for single level non-volatile memory cells (para 0170).
Regarding claim 13, Maejima discloses the method, further comprising: a bit line (any bit line BL0-BLn; fig. 2) connected to each non-volatile memory cell of the plurality of non-volatile memory cells positioned in different regions, the control circuit is configured to sequentially sense data (data is read out sequentially from page to page; para 0165) from the non-volatile memory cells positioned in different regions and connected to the bit line (fig. 11, 15) without recharging the voltage applied to the first word line (i.e. VSLCV applied to WL0 remains constant; fig. 15), the control circuit includes multiple latches connected to the bit line (fig. 9), the control circuit is configured to store sensed data from the non-volatile memory cells positioned in different regions and connected to the bit line (para 0137-0140) such that sensed data from different non-volatile memory cells is stored in different latches (different cells MT0-MT7 connected to different bit lines BL0-BLn, each respective bit line BL connected to different latch circuits to store sensed data in different latches; para 0137).
Regarding claim 14, Maejima discloses a method, comprising:
applying a word line voltage (during a read operation, apply a voltage VSLCV; fig. 15 para 0104) to a selected word line (WL0, i.e. selected word line; para 0165) connected to selected non-volatile memory cells (“blocks BLK (BLK0 to BLK3) which are each a grouping of nonvolatile memory cells [MT0 to MT7]” para 0036, further, WL0 connected to selected cells MT0; fig. 2) in different regions of non-volatile memory cells (i.e. different NAND string regions 17 including non-volatile memory cells MT0-MT7; fig. 2), each region of the different regions (i.e. each NAND string regions 17) includes a separate and independently controlled (i.e. via row decoders 11-0 to 11-3; fig. 1, 3) selection line (“selection gate lines SGD and SGS are independent for each of memory groups GP0 to GP3” para 0048) that selects and enables memory operations for the respective region (i.e. to select and enable in accordance with switching transistors of a row decoder; fig. 3);
while continuing to apply the word line voltage (i.e. VSLCV applied to WL0 remains constant; fig. 15) to the selected word line (WL0), sequentially (i.e. during time period(s) t0-t1, t1-t2, t2-t3…; fig. 15) and separately toggling on and then off (i.e. switching on/off; fig. 3, 15) each of the separate and independently controlled selection lines (i.e. during a read out; fig. 15); and
sensing data (i.e. via a sense amplifier) in the selected non-volatile memory cells (“sense amplifier 13 senses and amplifies the data read out from the memory cells when reading out the data” para 0039) in the different regions (NAND string regions 17) when respective separate and independently controlled selection lines are toggled on (i.e. switched on; fig. 15).
Regarding claim 15, Maejima discloses the method, wherein: the sensing data comprises sensing data in the selected non-volatile memory cells in the different regions that are connected to a same bit line (a same bit line having a first and second read out; para 0134) when respective separate and independently controlled selection lines are toggled on (i.e. switched on; fig. 15).
Regarding claim 16, Maejima discloses the method, further comprising: recharging the same bit line multiple times (i.e. charged during first and second read out; para 0134) while sensing data in the selected non-volatile memory cells connected to the same bit line in the different regions (para 0134).
Regarding claim 17, Maejima discloses the method, wherein: the sensing data comprises sensing data in the selected non-volatile memory cells in the different regions without recharging the selected word line (i.e. VSLCV applied to WL0 remains constant; fig. 15).
Regarding claim 18, Maejima discloses a non-volatile storage apparatus, comprising:
a plurality of non-volatile memory cells (“blocks BLK (BLK0 to BLK3) which are each a grouping of nonvolatile memory cells” para 0036);
a bit line (any bit line BL0-BLn; fig. 2) connected to each non-volatile memory cell (i.e. each MT0-MT7; fig. 2) of the plurality of non-volatile memory cells;
a word line (any word line WL0-WL7; fig. 2) connected to each non-volatile memory cell (i.e. each MT0-MT7) of the plurality non-volatile memory cells; and
a control circuit (12; fig. 3) connected to the bit line and the word line (any word line WL0-WL7; para 0097), the control circuit (12) is configured to apply one or more voltages to the word line (during a read operation, apply a voltage VSLCV to WL0; fig. 15 para 0104) that are in a first range of voltages (a range of voltages generated by voltage generation circuit 15, i.e. VPGMH, VREADH, VPASS, and VSLCV; para 0097) associated with testing for a particular data state (VSLCV is applied in testing to verify for a data state having a threshold voltage; fig. 13 para 0143) and sequentially sense data (“read out in order [i.e. sequentially] from the pages PG0 to PG11” fig. 14, 15, para 0165) from multiple non-volatile memory cells (MT0-MT7) connected to the bit line (para 0134) while continuing to apply one or more voltages to the word line (i.e. VSLCV applied to WL0 remains constant; fig. 15) that are in the first range of voltages (VPGMH, VREADH, VPASS, and VSLCV) associated with testing for the particular data state (fig. 13).
Regarding claim 19, Maejima discloses the non-volatile storage apparatus, further comprising: a plurality of separate and independently controlled (i.e. via row decoders 11-0 to 11-3; fig. 1, 3) selection lines (“selection gate lines SGD and SGS are independent for each of memory groups GP0 to GP3” para 0048) connected to the non-volatile memory cells, each non-volatile memory cell (i.e. each MT0-MT7) of the plurality non-volatile memory cells is connected to a different separate and independently controlled selection line (i.e. MT0-MT7, each coupled in series of a NAND string 17, of GP0 is connected to SGD0/SGS0, another MT0-MT7, each coupled in series of another NAND string region 17, of GP1 is connected to SGD1/SGS1, …; fig. 2), the control circuit (12) is configured to sequentially sense data from multiple non-volatile memory cells connected to the bit line when a respective separate and independently controlled selection line is toggled on (i.e. switched on; para fig. 15).
Regarding claim 20, Maejima discloses the non-volatile storage apparatus, wherein: the control circuit is configured to only toggle on one separate and independently controlled selection line at a time (fig. 15).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Maejima (US 2014/0254270) in view of Hosono (US 2017/0040065).
Regarding claim 10, Maejima does not expressly disclose a non-volatile storage apparatus, wherein the control circuit is configured to: receive a command from a memory controller to perform a read operation, the command includes a configurable data field that indicates which regions of the block are to be read.
Hosono discloses receive a command from a memory controller to perform a read operation (para 0046), the command includes a configurable data field (C0 “00h”; fig. 8A) that indicates which regions of the block are to be read (i.e. “indicates the address of memory cell MS that performs the read operation” para 0150, the memory cell essentially of a region of a block).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Maejima is modifiable as taught by Hosono for the purpose of facilitating data accessing schemes by improving the overall speed, which my reduce power consumption (para 0190-0193 of Hosono).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Maejima (US 2014/0254270) in view of Yang (US 2023/0012977).
Regarding claim 11, Maejima discloses the non-volatile storage apparatus, wherein: the plurality of non-volatile memory cells are part of a three dimensional memory structure (para 0032).
Maejima does not expressly disclose having multiple payers stacked vertically including layers for word lines, a layer for a source side selection line and a layer for a drain side selection line; the layers for word lines span all of the regions of the different regions of non-volatile memory cells; and the layer for a drain side selection line is divided into electrically isolated portions such that each portion comprises one of the separate and independently controlled selection lines.
Yang discloses having multiple layers stacked vertically including layers for word lines (fig. 4B-4J), a layer for a source side selection line (i.e. of selection gate SGS; fig. 4C); and a layer for a drain side selection line (i.e. of selection gate SGD; fig. 4C); the layers for word lines span all of the regions of the different regions of non-volatile memory cells (fig. 4B); and the layer for a drain side selection line is divided into electrically isolated portions such that each portion comprises one of the separate and independently controlled selection lines (para 0107-0108).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Maejima is modifiable as taught by Yang for the purpose of facilitating data accessing schemes by allowing separate control of each block and corresponding elements (para 0108 of Yang), which in turn allows for more flexibility in any particular application of operating parameters.
Conclusion
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/UYEN SMET/
[AltContent: connector] Primary Examiner, Art Unit 2824