Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the Applicant Election filled on 12/29/2025. Currently, claims 1-4, 6-11 and 13-22 are pending in the application. Claims 5, 12 and 23-28 have been cancelled.
Election/Restrictions
Applicant's election with traverse of Species V (Figures 9-10), claims 1-4, 6-11 and 13-22, in the reply filed on 12/29/2025 is acknowledged, there being no allowable generic or linking claim. The first traversal is on the ground(s) that the examination of all the Species would not present an undue burden on the Examiner, and respectfully request reconsideration and withdrawal of the Restriction Requirement.
This is not found persuasive and the Examiner has already established burden (as defined in M.P.E.P. 808.02) in the restriction requirement dated 11/26/2025. There is a search and/or examination burden for the patentably distinct species or device/method claims, wherein they require a different field of search (e.g., searching different classes/subclasses or electronic resources or non-patent language, or deploying different search queries); and/or the prior art applicable to one invention would not likely be applicable to another; and/or the inventions are likely to raise different non-prior art issues under 35 U.S.C 101 and/or 35 U.S.C 112, first paragraph. Therefore, the requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 6-11 and 13-22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Son et al (US 20210134809 A1).
Regarding claim 1, Figure 1 of Son discloses a semiconductor device comprising:
a first active pattern (104, left one, Figure 1B, [0031]) and a second active pattern (104, right one, Figure 1B) extending in a first direction (D1, Figure 1A, [0019]) and arranged in a second direction (D2, [0021]) intersecting the first direction, each of the first active pattern and the second active pattern including a first edge portion (at 412, left one, [0035], Figure 1B) and a second edge portion (at 412 right one) spaced apart from each other in the first direction (D1);
a first storage node pad (415, left one, [0038]) and a first storage node contact (417+418, [0038]) sequentially arranged on the first edge portion of the first active pattern; and
a second storage node pad (415, right one on BC, [0038]) and a second storage node contact (417+418 on BC, [0038]) sequentially arranged on the second edge portion of the second active pattern, wherein each of the first storage node contact and the second storage node contact includes a metal material (418 is Tungsten, [0041]).
Regarding claim 2, Figure 1 of Son discloses that the semiconductor device of claim 1, wherein each of the first storage node pad (415, left one) and the second storage node pad (415 on BC, right one, [0040]) independently include at least one of silicon and a metal material ([0040]).
Regarding claim 3, Figure 1 of Son discloses that the semiconductor device of claim 1, further comprising: a fence pattern (124, [0034]) between the first storage node contact and the second storage node contact, wherein the fence pattern separates the first storage node contact and the second storage node contact (418, [0040]) from each other in a third direction (D3) intersecting the first direction and the second directions (please see Figure 1A).
Regarding claim 4, Figure 1 of Son discloses that the semiconductor device of claim 3, wherein the fence pattern (124) includes at least one of silicon oxide, silicon nitride, silicon oxycarbide, and silicon oxy-carbonitride ([0023] and [0034]).
Regarding claim 6, Figure 1 of Son discloses that the semiconductor device of claim 1, further comprising: a first closed spacer (405-409, left one, [0057]) surrounding the first storage node contact (418) in a plan view; and a second closed spacer (405-409, right one, [0057]) surrounding the second storage node contact (418) in the plan view.
Regarding claim 7, Figure 1 of Son discloses that the semiconductor device of claim 6, wherein each of the first closed spacer (405-409) and the second closed spacer independently include at least one of silicon oxide, silicon nitride, silicon oxycarbide, and silicon oxy-carbonitride ([0060]).
Regarding claim 8, Figure 1 of Son discloses that the semiconductor device of claim 6, wherein the first closed spacer (405-409) comprises: a first closed sub-spacer surrounding the first storage node contact in the plan view; and a second closed sub-spacer between the first storage node contact and the first closed sub-spacer, and wherein the first closed sub-spacer and the second closed sub-spacer include different materials (considering different material in different portion of spacer as the claim is not specific about the sub-spacer location, [0049]).
Regarding claim 9, Figure 1 of Son discloses that the semiconductor device of claim 1, further comprising: a first bit line (BL, left one, Figure 1A, [0030]) on the first active pattern extending in a third direction (D3) intersecting the first direction and the second direction; and a second bit line (BL, right one) on the second active pattern extending in the third direction, wherein the first storage node contact and the second storage node contact (418) are between the first bit line and the second bit line (please see Figure 1B).
Regarding claim 10, Figure 1 of Son discloses that the semiconductor device of claim 9,further comprising: line spacers (404, [0033]) disposed between the first bit line (BL) and the first storage node contact (418) and between the second bit line and the first storage node contact, respectively.
Regarding claim 11, Figure 1 of Son discloses that the semiconductor device of claim 9, further comprising: a fence pattern (124, [0034]) between the first storage node contact and the second storage node contact; and sacrificial patterns (406) disposed between the first bit line and the fence pattern and between the second bit line and the fence pattern, respectively.
Regarding claim 13, Figure 1 of Son discloses that the semiconductor device of claim 1, further comprising: a third active pattern (please see for more 104 in Figure 1A) adjacent to the second active pattern in a third direction intersecting the first direction and the second direction; and a dummy word line (WL, [0022] and [0034]) extending in the second direction between the second active pattern and the third active pattern.
Regarding claim 14, Figure 1 of Son discloses that the semiconductor device of claim 1, wherein each of the first active pattern (104) and the second active pattern further includes a center portion between the respective first edge portion and the respective second edge portion, and the semiconductor device further comprises: a bit line node pad (312, [0031]) on each of the center portions of the first active pattern and the second active pattern.
Regarding claim 15, Figure 1 of Son discloses a semiconductor device comprising:
a first active pattern (104, left one, Figure 1B, [0019]) and a second active pattern (104, right one, Figure 1B) extending in a first direction (D1, Figure 1A) and arranged in a second direction (D2, Figure 1A) intersecting the first direction, each of the first active pattern and the second active pattern including a first edge portion (at 412, left side) and a second edge portion (at 412, right one) spaced apart from each other in the first direction (D1);
a first storage node pad (415, [0038]) and a first storage node contact (417+418, left one, [0038]) sequentially arranged on the first edge portion of the first active pattern;
a second storage node pad (415 on BC, right one, [0038]) and a second storage node contact (417+418, right one, [0038]) sequentially arranged on the second edge portion of the second active pattern;
a first closed spacer (406-409, at left side, [0057]) surrounding the first storage node contact in a plan view; and
a second closed spacer (406-409, at right side, [0057]) surrounding the second storage node contact in the plan view.
Regarding claim 16, Figure 1 of Son discloses that the semiconductor device of claim 15, wherein each of the first storage node contact and the second storage node contact includes a metal material (417+418, [0041]).
Regarding claim 17, Figure 1 of Son discloses that the semiconductor device of claim 15, wherein each of the first storage node pad and the second storage node pad independently include at least one of silicon and a metal material (415 includes metal, [0040]).
Regarding claim 18, Figure 1 of Son discloses that the semiconductor device of claim 15, wherein the first closed spacer (406-409, at left side, [0057]) comprises: a first closed sub-spacer surrounding the first storage node contact; and a second closed sub-spacer between the first storage node contact and the first closed sub-spacer, and wherein the first closed sub-spacer and the second closed sub-spacer include different materials (considering different material in different portion of spacer as the claim is not specific about the sub-spacer, [0049]).
Regarding claim 19, Figure 1 of Son discloses that the semiconductor device of claim 15, further comprising: a fence pattern (124, [0034]) between the first storage node contact and the second storage node contact (417+418), wherein the fence pattern is spaced apart from the first storage node contact by the first closed spacer (404-409) and is spaced apart from the second storage node contact by the second closed spacer.
Regarding claim 20, Figure 1 of Son discloses that the semiconductor device of claim 15, further comprising: a first bit line (BL, Figure 1A, [0018] and [0031]) on the first active pattern and extending in a third direction (D3) intersecting the first direction and the second direction; and a line spacer (404, [0033]) extending from between the first bit line and the second storage node contact to between the first bit line and the first storage node contact (417+418).
Regarding claim 21, Figure 1 of Son discloses a semiconductor device comprising:
a first active pattern (104, left one, Figure 1B, [0019]) and a second active pattern (104, right one, Figure 1B) extending in a first direction (D1, Figure 1A) and arranged in a second direction (D2, Figure 1A) intersecting the first direction, each of the first active pattern and the second active pattern including a first edge portion (at 412, left side) and a second edge portion (at 412, right side) spaced apart from each other in the first direction and a center portion between the first edge portion and the second edge portion;
a pair of word lines (WL, [0034]) extending in the second direction (D2) to intersect the first active pattern and the second active pattern;
a first storage node pad (415, left one, [0038]) and a first storage node contact (417+418a+b, left one, [0038]) sequentially provided on the first edge portion of the first active pattern;
a second storage node pad (415, right one, [0038]) and a second storage node contact (417+418a+b, right one, [0038]) sequentially provided on the second edge portion of the second active pattern;
a first bit line (BL, left one, Figure 1A, [0031]) on the first active pattern and extending in a third direction (D3, Figure 1A) intersecting the first direction and the second directions;
a second bit line (BL, right one, Figure 1A, [0031]) extending in the third direction on the second active pattern;
a fence pattern (124, [0034]) between the first storage node contact and the second storage node contact;
landing pads (418c, [0038]) on the first storage node contact (417+418a+b) and the second storage node contact; and
data storage patterns (CAP, [0044]) on the landing pads, wherein
the first edge portion (at 414, left side one) of the first active pattern and the first edge portion of the second active pattern are adjacent to each other in the second direction,
the first edge portion of the first active pattern and the second edge portion (at 414, right side one) of the second active pattern are adjacent to each other in the third direction (D3), and
each of the first storage node contact and the second storage node contacts includes a metal material (418, [0041]).
Regarding claim 22, Figure 1 of Son discloses that the semiconductor device of claim 21, wherein each of the landing pads (415) is shifted from a corresponding one of the first storage node contact (418c, left one) and the second storage node contact (418c, right one) in the third direction or an opposite direction to the third direction ([0042]).
Examiner Notes
A reference to specific paragraphs, columns, pages, or figures in a cited prior art reference is not limited to preferred embodiments or any specific examples. It is well settled that a prior art reference, in its entirety, must be considered for all that it expressly teaches and fairly suggests to one having ordinary skill in the art. Stated differently, a prior art disclosure reading on a limitation of Applicant's claim cannot be ignored on the ground that other embodiments disclosed were instead cited. Therefore, the Examiner's citation to a specific portion of a single prior art reference is not intended to exclusively dictate, but rather, to demonstrate an exemplary disclosure commensurate with the specific limitations being addressed. In re Heck, 699 F.2d 1331, 1332-33,216 USPQ 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 USPQ 275, 277 (CCPA 1968)). In re: Upsher-Smith Labs. v. Pamlab, LLC, 412 F.3d 1319, 1323, 75 USPQ2d 1213, 1215 (Fed. Cir. 2005); In re Fritch, 972 F.2d 1260, 1264, 23 USPQ2d 1780, 1782 (Fed. Cir. 1992); Merck& Co. v. BiocraftLabs., Inc., 874 F.2d 804, 807, 10 USPQ2d 1843, 1846 (Fed. Cir. 1989); In re Fracalossi, 681 F.2d 792,794 n.1, 215 USPQ 569, 570 n.1 (CCPA 1982); In re Lamberti, 545 F.2d 747, 750, 192 USPQ 278, 280 (CCPA 1976); In re Bozek, 416 F.2d 1385, 1390, 163 USPQ 545, 549 (CCPA 1969).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAJA AHMAD whose telephone number is (571)270-7991. The examiner can normally be reached on Monday-Friday, 8:00 AM - 5:00 PM (Eastern Time).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, GAUTHIER STEVEN B, can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHAJA AHMAD/Primary Examiner, Art Unit 2813