DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5-7, 9-10, 12-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xie et al (US Publication No. 2022/0406715).
Regarding claim 1, Xie discloses a semiconductor device comprising: a stack of nanostructure material layers Fig 9A, 18 or Fig 11, 18, wherein a gate structure Fig 11, 92, is present on a channel region portion for the stack of nanostructure material layers Fig 11; first source and drain regions Fig 12A, 1210 are present on a first region of the channel region portion Fig 12A, wherein the first source and drain regions are comprised of a first epitaxial semiconductor material ¶0077 that has a confinement sidewall spacer Fig 12B, 54 in direct contact with sidewalls of the first epitaxial semiconductor material defining a lateral dimension for the epitaxial semiconductor material Fig 12B; and second source and drain regions are present on a second region of the channel region portion for the stack of nanostructure material layer Fig 12A-12C, wherein the second source and drain regions are composed of a second epitaxial semiconductor material that partially extends over the confinement sidewall spacer ¶0067.
Regarding claim 2, Xie discloses wherein a power contact extends from the second source and drain regions to a power rail, wherein the power contact is separated from the first source and drain regions by the confinement sidewall spacer Fig 14B ¶0085-0087.
Regarding claim 3, Xie discloses wherein the first source and drain regions are connected to a power rail by a backside contact Fig 13A-14D.
Regarding claim 5, Xie discloses a dielectric nanosheet geometry spacer Fig 12A-12C, 72 is present between the first and second source and drain regions of the stack of nanostructure material layers Fig 12A-12C.
Regarding claim 6, Xie discloses the first source and drain regions and the gate structure are configured to provide a gate all around nanosheet device Fig 11-14D.
Regarding claim 7, Xie discloses the first epitaxial semiconductor material does not extend above end surfaces of the confinement sidewall spacer Fig 13B-14D.
Regarding claim 9, Xie discloses the second epitaxial semiconductor material extends above at least one end surface of the confinement sidewall spacer to provide a partially exposed sidewall for the second epitaxial semiconductor material Fig 13B-14D.
Regarding claim 10, Xie discloses semiconductor device comprising: a stack of nanostructure material layers Fig 9A, 18 or Fig 11, 18, wherein a gate structure Fig 11, 92 is present on a channel region portion for the stack of nanostructure material layers Fig 11; bottom source and drain regions present on a first side of the channel region portion, wherein the bottom source and drain regions are composed by a first epitaxial semiconductor material ¶0077 that has a confinement sidewall spacer Fig 12B, 54 in direct contact with sidewalls of the first epitaxial semiconductor material defining a lateral dimension for the epitaxial semiconductor material Fig 12B-12C; upper source and drain regions present on a second side of the channel region portion for the stack of nanostructure material layers Fig 12A-12C, wherein the upper source and drain regions are composed of a second epitaxial semiconductor material that partially extends over the confinement sidewall spacer Fig 12A-12C; and a power contact extends from the upper source and drain regions to a backside power rail contact Fig 13A-13C, wherein the power contact is separated from a lower source and drain regions by the confinement sidewall spacer Fig 13A-14B.
Regarding claim 12, Xie discloses the second epitaxial semiconductor material extends above at least one end surface of the confinement sidewall spacer to provide a partially exposed sidewall for the second epitaxial semiconductor material Fig 13A-14B.
Regarding claim 13, Xie discloses a method of forming a semiconductor device comprising: forming suspended channel regions Fig 9A, 18 or Fig 11, 18; forming lower source and drain regions using a first epitaxial growth process ¶0077on a lower portion of the suspended channel regions Fig 12A-12B, wherein lateral growth of epitaxial semiconductor material ¶0077is confined with a confinement sidewall spacer Fig 12B, 54; and forming upper source and drain regions Fig 13A-13C using a second epitaxial growth process¶0067, wherein the epitaxial semiconductor material for the upper source and drain regions extends over the confinement sidewall spacer Fig 13A-14B.
Regarding claim 14, Xie discloses forming a power contact that extends from the upper source and drain regions to a backside power rail contact Fig 13A-14D, wherein the power contact is separated from the lower source and drain regions by the confinement sidewall spacer Fig 13A-14D.
Regarding claim 15, Xie discloses forming a backside contact on the lower source and drain regions, and connecting the backside contact to a backside power rail Fig 14C-14D.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4, 8, 11, 20-25 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al (US Publication No. 2022/0406715) in view of Wang et al (US Publication No. 2022/0359514).
Regarding claim 4, Xie discloses all the limitations but silent on the type of device. Whereas Wang discloses wherein the second source and drain regions and the gate structure are configured to provide a forksheet device Fig 20A. Xie and Wang are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Xie because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Xie and incorporate the teachings of Wang as an alternative type of device known in the art as a matter of design choice.
Regarding claim 8, Wang discloses wherein the first epitaxial semiconductor material is fully confined by the confinement sidewall spacer Fig 17A, 128/157.
Regarding claim 11, Wang discloses wherein the first epitaxial semiconductor material does not extend above end surfaces of the confinement sidewall spacer, and is fully confined by the confinement sidewall spacer Fig 17A, 128/157.
Regarding claim 20, Xie discloses semiconductor device comprising: a stack of nanostructure material layers Fig 9A, 18 or Fig 11, 18, wherein a gate structure Fig 11, 92 is present on a channel region portion for the stack of nanostructure material layers; bottom source and drain regions Fig 12A, 1210 are present on a bottom region of the channel region portion, wherein the bottom source and drain regions are comprised of a first epitaxial semiconductor material ¶0077 that has a confinement sidewall spacer Fig 12B, 54 in direct contact with sidewalls of the first epitaxial semiconductor material defining a lateral dimension for the epitaxial semiconductor material Fig 12B; and top source and drain regions Fig 12A, 80 are present on a top region of the channel region portion for the stack of nanostructure material layer Fig 12A-14D, wherein the top source and drain regions are composed of a second epitaxial semiconductor material ¶0067 that partially extends over the confinement sidewall spacer Fig 12B, 54. Xie discloses all the limitations but silent on the type of device. Whereas Wang discloses wherein the bottom source and drain regions and the gate structure are configured to provide a forksheet device Fig 20A. Xie and Wang are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Xie because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Xie and incorporate the teachings of Wang as an alternative type of device known in the art as a matter of design choice.
Regarding claim 21, Xie discloses wherein a power contact extends from the top source and drain regions to a power rail, wherein the power contact is separated from the bottom source and drain regions by the confinement sidewall spacer Fig 14B ¶0085-0087.
Regarding claim 22, Xie discloses wherein the bottom source and drain regions are connected to a power rail by a backside contact Fig 13A-14D.
Regarding claim 23, Xie discloses a dielectric nanosheet geometry spacer Fig 12A-12C, 72 is present between the bottom region and second regions of the stack of nanostructure material layers Fig 12A-12C.
Regarding claim 24, Wang discloses the first epitaxial semiconductor material does not extend above end surfaces of the confinement sidewall spacer, and is fully confined by the confinement sidewall spacer Fig 17A, 128/157.
Regarding claim 25, Xie discloses wherein the second epitaxial semiconductor material extends above at least one end surface of the confinement sidewall spacer to provide a partially exposed sidewall for the second epitaxial semiconductor material Fig 13A-14D.
Claims 16 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al (US Publication No. 2022/0406715) in view of Su et al (US Publication No. 2022/0271139).
Regarding claim 16, Xie discloses all the limitations but silent on the gate cut structure. Whereas Su discloses forming a gate structure, wherein an upper portion of the gate structure is cut and filled with a bilayer of a nitride containing liner and an oxide containing fill, the upper portion of the gate structure being cut and filled with dielectric material to reduce parasitic capacitance ¶0055 Fig 25B-1 and Fig 25C-1. Xie and Su are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Xie because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Xie and incorporate the teachings of Su to improve device performance.
Regarding claim 19, Xie discloses the lower source and drain regions and the gate structure are configured to provide a gate all around nanosheet device Fig 13A-14D.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Xie et al (US Publication No. 2022/0406715) in view of Su et al (US Publication No. 2022/0271139) and in further view of Wang et al (US Publication No. 2022/0359514).
Regarding claim 18, Xie discloses all the limitations but silent on the type of device. Whereas Wang discloses wherein the lower source and drain regions and the gate structure are configured to provide a forksheet device Fig 20A. Xie and Wang are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Xie because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Xie and incorporate the teachings of Wang as an alternative type of device known in the art as a matter of design choice.
Allowable Subject Matter
Claim 17 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/CHRISTINE A ENAD/ Primary Examiner, Art Unit 2811