DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant election of group I, claims 1-10, without traverse is acknowledged. Claims 11-15 are withdrawn from consideration.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections und`er this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Takao (US 2007/0001289), (hereinafter, Takao).
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RE Claim 1, Takao discloes a semiconductor device and a method of making the same. Takao discloes in FIGS. 1-6 a method of manufacturing a semiconductor circuit “field effect transistor FET”, referring to FIGS. 6A-6C [0053], the method comprising:
forming a layer stack comprising a device layer 16 and an insulator layer 14 [abstract, 0039, 0041, 0055, 062] wherein the device layer 16 “silicon active layer” comprises electronic elements “field effect transistor FET”, and wherein the insulator layer 14 is adjacent to a back surface of the device layer 16 “silicon active layer”, referring to FIG. 6C;
adhesive bonding, using mounting material 53, a spacer disk 62 “heat spreader” on the layer stack to a side of the insulating layer 14 opposite the device layer 16 “silicon active layer”, wherein the spacer disk 62 and the layer stack form a wafer composite [0077-0079], referring to FIGS.6A-6C. Examiner notes that the heat spreader disk 62 is indirectly bonded to a side of the insulating layer 14, hence meeting the claimed limitation as the claim language, according to the broadest reasonable interpretation can be direct or indirect boding; and
dividing the wafer composite into a plurality of individual semiconductor chips, wherein each semiconductor chip 2 comprises a portion of the layer stack and a portion of the spacer disk 62 “heat spreader”, referring to FIG. 6C [0079]. Since the dicing process is performed after the heat spreader 62 “spacer” is attached to the device layer 16 “silicon active layer”, the claimed limitation is met.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
Claim(s) 2 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takao (US 2007/0001289), (hereinafter, Takao) in view of Shinohara et al. (US 7,641,967), (hereinafter, Shinohara).
RE Claim 2, Takao discloes a method, wherein a thickness of the device layer 16 “silicon active layer” is 2 µm -10 µm, which is within the claimed range of at most 100µm [0039],
Furthermore, Takao discloes that the support substrate 12 is around 50 microns, the oxide layer 14 is 0.3-1 micron and the interconnect layer 20 is 1-3 microns, wherein the layers’ thicknesses and type impact the thermal conduction of the overall chip structure [0055], however, Takao does not discloes wherein a sum of a thickness of the layer stack and a thickness of the spacer disk is at least 100µm.
However, it would have been obvious to one having ordinary skill in the art at the effective filing date the invention was filed to achieve the claimed overall thickness, absent unexpected results, in order to the achieve the best chip thermal performance , since it has been held that discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233; In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980); In re Huang, 100 F.3d 135, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996).
RE Claim 9, Takao discloes a semiconductor device and a method of making the same. Takao discloes in FIGS. 1-6 a method of manufacturing a semiconductor circuit “field effect transistor FET”, referring to FIGS. 6A-6C [0053], the method comprising:
forming a layer stack comprising a device layer 16 and an insulator layer 14 [abstract, 0039, 0041, 0055, 062] wherein the device layer 16 “silicon active layer” comprises electronic elements “field effect transistor FET”, and wherein the insulator layer 14 is adjacent to a back surface of the device layer 16 “silicon active layer”, referring to FIG. 6C;
adhesive bonding, using mounting material 53, a spacer disk 62 “heat spreader” on the insulator layer 14 on a side opposite the device layer 16 “silicon active layer”, wherein the spacer disk 62 and the layer stack form a wafer composite [0077-0079], referring to FIGS.6A-6C. Examiner notes that the heat spreader disk 62 is indirectly bonded to a side of the insulating layer 14, hence meeting the claimed limitation; and
dividing the wafer composite into a plurality of individual semiconductor chips, wherein each semiconductor chip 2 comprises a portion of the layer stack and a portion of the spacer disk 62 “heat spreader”, referring to FIG. 6C [0079]. Since the dicing process is performed after the heat spreader 62 “spacer” is attached to the device layer 16 “silicon active layer”, the claimed limitation is met.
Takao does not discloes an adhesive tape, and the spacer disk 62 “heat spreader” on a side of the adhesive tape opposite the layer stack.
However, in a related art Shinohara discloses a pressure-sensitive, heat-resistant adhesive tape 13, i.e. masking tape, for large scale chip-scale packaging, wherein a partially cross-linked polymer “adhesive layer” on the adhesive tape for die-bonding on a leading frame [Claim 1, columns 8 and 9].
Therefore, it would have been obvious for one of ordinary skill in the art, at the effective filing date of the instant application to use the adhesive tape of Shinohara disclosure as the adhesive bonding layer whererein applying an adhesive tape to the layer stack a side of the insulating layer 14 opposite the device layer, wherein the adhesive tape, substituting bonding layer 53, comprises a partially crosslinked resin of Shinohara disclosure in order to attach the spacer disk 62 “heat spreader” to the support structure 12 of the chip 2, as well-known bonding and die attachment method in order to achieve wafer-based packaging.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takao (US 2007/0001289), (hereinafter, Takao) in view of Rupp et al. (US 2017/0033011), (hereinafter, Rupp).
RE Claim 10, Takao discloes a semiconductor device and a method of making the same. Takao discloes in FIGS. 1-6 a method of manufacturing a semiconductor circuit “field effect transistor FET”, referring to FIGS. 6A-6C [0053], the method comprising:
providing a semiconductor chip, wherein the semiconductor chip 2 comprises a device layer portion 16 “silicon active layer”, an insulator layer 14 portion in contact with a back surface of the device layer portion 16 “silicon active layer”, referring to FIG. 6C [abstract, 0039, 0041, 0055, 062],
an adhesive layer 53 “mounting material”, which is functionally equivalent to an adhesive layer since it is bonding the support layer 12 to the heat spreader 62 [0077 and 0079], formed on a side of the insulator layer 14 portion opposite the device layer portion 16, referring to FIG. 6C. examiner notes that the functionally equivalent adhesive layer, according to the broadest reasonable interpretation can be directly or indirectly bonded, and
a spacer layer 62 “heat spreader” formed on a side of the adhesive layer 53 opposite the insulator layer portion 14, wherein electronic elements “field effect transistors FET” are formed in the device layer portion 16 [0053, 0058, 0059, 0074], and
forming electrical connections 20 to device terminals.
Takao does not disclose contact pads 82 are formed on a contact side surface of the device layer portion; and
forming the electrical connections 20 between the contact pads and device terminals.
However, in the same field of endeavor, Rupp discloses a method of making a semiconductor device, wherein front-side metallization 3 is electrically connected to a pad structure 57′ of the lead structure 57.
Therefore, it would have been obvious for one of ordinary skill in the art, at the effective filing date of the instant application to use pad structure, as a well-known interconnect structure for forming the electrical connections 20 between the contact pads and device terminals and forming interconnect structure to other devices.
Allowable Subject Matter
Claims 16-17 are allowed.
Claims 3-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including wherein adhesive bonding the spacer disk to the side of the insulator layer opposite the device layer comprises: applying an adhesive tape to the layer stack on the side of the insulator layer opposite the device etching of the coating prior to applying the loosening agent as disclosed in Claim 3. The examiner considers that the adhesive tape is directly applied to the side of the insulator layer opposite the device layer.
Response to Arguments
Applicant's arguments filed 04/17/2026, with respect to Claims 9 and 10 have been fully considered but they are not persuasive. In the instant case, Examiner notes that the heat spreader disk 62 is indirectly bonded to a side of the insulating layer 14, hence meeting the claimed limitation as the claim language, according to the broadest reasonable interpretation can be direct or indirect boding. Therefore, the claims rejection is maintained.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
In the instant case, NONOGAKI (US 2011/0089524) discloses a semiconductor device and a method of manufacturing the same capable of reducing variations in the thickness of a semiconductor device are provided. The amount of oxygen implanted ions is less than the amount of implanted oxygen ions in the conventional epitaxial SIMOX wafers. Oxygen is ion-implanted into the surface layer of a silicon wafer from the surface of the wafer. Then, by heat treating the wafer, a thinning stop layer, which is an imperfect buried oxide film, is formed along the entire plane of the wafer. As a result, variation of the thickness of the semiconductor device formed in an active layer can be reduced, since the, the reliability of the accuracy of the end point of silicon wafer thinning is higher than that of a thinning using the conventional deep trench structure as an end point detector.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YASSER ABDELAZIEZ whose telephone number is (571)270-5783. The examiner can normally be reached Monday - Friday 9 am - 6 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at (571)270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YASSER A ABDELAZIEZ, PhD/Primary Examiner, Art Unit 2898
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