DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
Claim(s) 1-6, 8, 9, 10 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over BEYER et al. (EP-3951841), (hereinafter, BEYER) in view of Orita et al. (US 2012/0313199), (hereinafter, Orita) and in further view of Wang et al. ("Montmorillonite-Based Two-Dimensional Nanocomposites: Preparation and Applications," Molecules, 26, 2521, 2021), (hereinafter, Wang).
RE Claims 1 and 4, BEYER discloses in FIG. 7B a power semiconductor device 60, comprising:
a semiconductor body 10a comprising a first surface and a second surface, referring to FIG. 7B above;
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a first load terminal 30 “electrode layer” arranged on the first surface;
a second load terminal 35 “back-side electrode” arranged on the second surface;
an active region “AR” comprising at least one semiconductor cell configured to conduct a load current between the first load terminal 30 and the second load terminal 35;
an edge termination region “TR” between the active region and a chip 10a edge, referring to FIG. 7B; and
a thin film layer 40p “mold compound pattern” over at least parts of the edge termination region “TR” and/or over at least parts of the first load terminal 30, referring to FIG. 7B.
BEYER does not disclose the thin film layer 40P comprises a bulk material and a laminar filler compound.
However, in a related art, Orita discloses a passivation film for semiconductor devices such as solar cells, made of polymer compound have anionic group or a cationic group and a filler [abstract and 0021-0029], wherein the passivation film comprising a bulk material made of polyfluoroolefin resins having a structure in which part of fluorine atoms in a polyperfluoroolefin resin, which is inherently a UV curable resin, are substituted by hydrogen atoms, hence meeting the limitation of Claim 4 [0071], polyaryl ether sulfone, polyphenylene oxide, polycarbonate, polyurethane, polyamide, polyimide, polyurea, polysulfone, polyacrylate derivatives, polymethacrylate derivatives, and polystyene derivatives and a filler comprising montmorillonite, which is considered a laminar filler, a nanoclay, hence meeting the limitation of Claim 10, [0131] or clay, hence meeting the claimed limitation.
Therefore, it would have been obvious for one of ordinary skill in the art, prior to the effective filing date of the instant application to use the passivation film of Orita disclosure as the composition of polymer compound material 40p of BEYER as an edge termination in order to reduce the cost and processing thermal budget and enhance protection of underlaying materials surface and isolating the base material of the semiconductor chip from external and corrosive environment.
Furthermore, BEYER in view of Orita don’t explicitly state that the laminar filler compound is arranged in a two-dimensional layered structure within the bulk material.
However, in a related art, Wang discloses Montmorillonite (Mt) of 2:1 type layered phyllosilicate mineral with nanoscale structure, large surface area, high cation exchange capacity and excellent adsorption capacity with Mt-based two-dimensional (2D) functional composite materials, such as Mt-metal hydroxides.
Therefore, it would have been obvious for one of ordinary skill in the art, prior to the effective filing date of the instant application, to have BEYER in view of Orita laminar filler arranged in a two-dimensional layered structure within the bulk material in order to enhance passivation properties of the passivation film and overcome composite materials deficiencies.
RE Claim 2, BEYER discloses power semiconductor device, wherein the first load terminal 30 and the second load terminal 35 both comprise one or more metal layers [0034].
RE Claim 3, BEYER discloses power semiconductor device, wherein the thin film layer 40 is over parts of the edge termination structure “TR” and the first load terminal as a passivation layer [0035].
RE Claim 5, BEYER does not disclose power semiconductor device, wherein the bulk material of the thin film layer comprises an imide-based, ethylene-based, propylene-based polymer, or a combination thereof.
However, Orita discloses a passivation film for semiconductor devices such as solar cells, wherein the bulk material of the thin film layer comprises an imide-based “polyimide” [0349], ethylene-based [0088] or a combination thereof.
Therefore, it would have been obvious for one of ordinary skill in the art, prior to the effective filing date of the instant application, to use similar imide-based compound such as polyimide in order to achieve the desired isolation of the base material of the semiconductor chip from external and corrosive environment.
Although Orita disclosure does not specify polyimide as being UV curable, examiner takes an Official Notice that UV curable polyimide is well-known in the art as a passivation for semiconductor devices.
Therefore, it would have been obvious for one of ordinary skill in the art, prior to the effective filing date of the instant application, to use similar UV curable imide-based compound such as UV curable polyimide in order to achieve the desired isolation of the base material of the semiconductor chip from external and corrosive environment with minimum thermal budget.
RE Claim 6, BEYER does not disclose power semiconductor device, wherein the laminar filler compound of the thin film layer has a hydrophobic-modified surface.
However, in a related art, Orita discloses a passivation film for semiconductor devices such as solar cells, made of polymer compound have anionic group or a cationic group and a filler [abstract and 0021-0029], wherein the passivation film comprising a bulk material made of polyfluoroolefin resin and a filler comprising montmorillonite, which inherently has hydrophobic-modified surface.
Therefore, it would have been obvious for one of ordinary skill in the art, prior to the effective filing date of the instant application to use the montmorillonite, as the thin film filler due to its well-known hydrophobic-modified surface in order to best protective properties of the edge-termination region of BEYER disclosed device.
RE Claim 8, BEYER in view of Orita do not disclose power semiconductor device, wherein the laminar filler compound of the thin film layer comprises a layered silicate.
However, in a related art, Wang discloses Montmorillonite (Mt) of 2:1 type layered phyllosilicate mineral with nanoscale structure, large surface area, high cation exchange capacity and excellent adsorption capacity with Mt-based two-dimensional (2D) functional composite materials, such as Mt-metal hydroxides [abstract].
Therefore, it would have been obvious for one of ordinary skill in the art, prior to the effective filing date of the instant application, to use the layered silica as the laminar filler of the BEYER in view of Orita thin film in order to improve the barrier properties of the thin film passivation layer that termination end region “TR”.
RE Claim 9, BEYER in view of Orita do not disclose power semiconductor device, wherein the content of the laminar filler compound in the thin film layer is at least 0.5 wt.-% and at most 5 wt.-%.
However, it would have been obvious to one having ordinary skill in the art prior to the effective filing date of the instant application to use the claimed laminar filler weight percentages, absent unexpected results, since it has been held that discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233; In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980); In re Huang, 100 F.3d 135, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996).
RE Claim 19, BEYER discloses power semiconductor device, wherein the thin film layer 40P in indirectly contacts the first surface of the semiconductor body 10a.
Claim(s) 16-18 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over BEYER et al. (EP-3951841), (hereinafter, BEYER) in view of Orita et al. (US 2012/0313199), (hereinafter, Orita) and in further view of Wang et al. ("Montmorillonite-Based Two-Dimensional Nanocomposites: Preparation and Applications," Molecules, 26, 2521, 2021), (hereinafter, Wang) and Nawani et al. ("Characterization of nanoclay orientation in polymer nanocomposite film by small-angle X-ray scattering," Polymer, Volume 51, Issue 22, Pages 5255-5266, 15 October 15th 2010), (hereinafter, Nawani).
RE Claim 16, BEYER in view of Orita do not disclose a power semiconductor device, wherein the laminar filler compound comprises particles with a two-dimensional planar orientation.
However, in a related art, Nawani discloses Montmorillonite-type clays composite materials and a study orientation distribution of layer-shaped nanoclays (e.g. organoclays and pristine clays) dispersed in a polymer matrix is an important parameter to control the properties of polymer nanocomposites. In this study, we demonstrate that the use of multi-directional 2-D small-angle X-ray scattering (SAXS), wherein the particles with a two-dimensional planar orientation [section 3.4, right-hand column, first paragraph].
Therefore, it would have been obvious for one of ordinary skill in the art, prior to the effective filing date of the instant application to have the laminar filler of BEYER in view of Orita particles of two-dimensional planar orientation in order to control properties of composite material such as gas diffusion within such layers, as Nawani disclosed in FIG. 12.
RE Claims 17, 18 and 21, BEYER in view of Orita do not disclose a power semiconductor device, wherein the two-dimensional layered structure comprises two or more layers of filler compounds arranged in a stacked structure within the bulk material of the thin film or wherein the laminar filler compound forms a three-dimensional network of integrated filler compounds that blocks or slows diffusion of gaseous compounds through a thickness of the thin film.
However, Nawani discloses Montmorillonite-type clays composite materials and a study orientation distribution of layer-shaped nanoclays, wherein the two-dimensional layered structure comprises two or more layers of filler compounds arranged in a stacked structure within the bulk material of the thin film, referring to FIG. 12 [sections 3.3 and 3.4].
Therefore, it would have been obvious for one of ordinary skill in the art, prior to the effective filing date of the instant application to have the laminar filler of BEYER in view of Orita particles of two-dimensional planar orientation in order to control properties of composite material such as gas diffusion within such layers, as Nawani disclosed in FIG. 12 [section 3.4].
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over BEYER et al. (EP-3951841), (hereinafter, BEYER) in view of Orita et al. (US 2012/0313199), (hereinafter, Orita) and in further view of Wang et al. ("Montmorillonite-Based Two-Dimensional Nanocomposites: Preparation and Applications," Molecules, 26, 2521, 2021), (hereinafter, Wang) and EBIHARA (US 2021/0118761), (hereinafter, EBIHARA).
RE Claim 20, BEYER in view of Orita do not disclose a power semiconductor device, further comprising a silicon nitride film between the thin film layer and the first surface of the semiconductor body.
However, in the same field of endeavor, EBIHARA discloses in FIG. 4 a power semiconductor device comprising silicon nitride film 15 “moisture resistant layer between a protective film 6 and a substrate 30 “SiC”.
Therefore, it would have been obvious for one of ordinary skill in the art, prior to the effective filing date of the instant application have a silicon nitride layer between the thin film layer and the first surface of the semiconductor body of BEYER in order enhance protection of semiconductor surface against moisture penetration.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YASSER ABDELAZIEZ whose telephone number is (571)270-5783. The examiner can normally be reached Monday - Friday 9 am - 6 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at (571)270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YASSER A ABDELAZIEZ, PhD/Primary Examiner, Art Unit 2898
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