DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant election of group I, species I “FIG. 3”, claims 1-10, without traverse, is acknowledged. Claims 11-15 are withdrawn from consideration.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 7 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, because the specification, while being enabling for having laminar fillers, does not reasonably provide enablement for “the laminar filler compound is oriented substantially parallel to a surface of the power semiconductor device.” The specification does not enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use of the invention commensurate in scope with these claims. In the instant, one of ordinary skill in the art, without undue experimentation, can achieve the filler structure, particularly the nanoclayer layered structure, to be particularly parallel to the to a surface of the power semiconductor device. The disclosure does not provide any description on how this can be achieved, as evidenced by Dulebova et al. (“Properties and Application of Polymer-Clay Nanocomposites,” American Journal of Polymer Science, 5(2): 47-53, 2015), which is provided by applicant IDS. Although examiner has raised the scope of enablement due to the disclosure insufficiency of the instant disclosure on how to achieve the claimed invention. However, Examiner will consider that the method described by Dulebova et al. may be sufficient to address the subject matter of Claim 7. Applicant explanation is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
Claim(s) 1-6, 9 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over BEYER et al. (EP-3951841), (hereinafter, BEYER) in view of Orita et al. (US 2012/0313199), (hereinafter, Orita).
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RE Claims 1 and 4, BEYER discloses in FIG. 7B a power semiconductor device 60, comprising:
a semiconductor body 10a comprising a first surface and a second surface, referring to FIG. 7B above;
a first load terminal 30 “electrode layer” arranged on the first surface;
a second load terminal 35 “back-side electrode” arranged on the second surface;
an active region “AR” comprising at least one semiconductor cell configured to conduct a load current between the first load terminal 30 and the second load terminal 35;
an edge termination region “TR” between the active region and a chip 10a edge, referring to FIG. 7B; and
a thin film layer 40p “mold compound pattern” over at least parts of the edge termination region “TR” and/or over at least parts of the first load terminal 30, referring to FIG. 7B.
BEYER does not disclose the thin film layer 40P comprises a bulk material and a laminar filler compound.
However, in a related art, Orita discloses a passivation film for semiconductor devices such as solar cells, made of polymer compound have anionic group or a cationic group and a filler [abstract and 0021-0029], wherein the passivation film comprising a bulk material made of polyfluoroolefin resins having a structure in which part of fluorine atoms in a polyperfluoroolefin resin, which is inherently a UV curable resin, are substituted by hydrogen atoms, hence meeting the limitation of Claim 4 [0071], polyaryl ether sulfone, polyphenylene oxide, polycarbonate, polyurethane, polyamide, polyimide, polyurea, polysulfone, polyacrylate derivatives, polymethacrylate derivatives, and polystyene derivatives and a filler comprising montmorillonite, which is considered a laminar filler, a nanoclay, hence meeting the limitation of Claim 10, [0131] or clay, hence meeting the claimed limitation.
Therefore, it would have been obvious for one of ordinary skill in the art, prior to the effective filing date of the instant application to use the passivation film of Orita disclosure as the composition of polymer compound material 40p of BEYER as an edge termination in order to reduce the cost and processing thermal budget and enhance protection of underlaying materials surface and isolating the base material of the semiconductor chip from external and corrosive environment.
RE Claim 2, BEYER discloses power semiconductor device, wherein the first load terminal 30 and the second load terminal 35 both comprise one or more metal layers [0034].
RE Claim 3, BEYER discloses power semiconductor device, wherein the thin film layer 40 is over parts of the edge termination structure “TR” and the first load terminal as a passivation layer [0035].
RE Claim 5, BEYER does not disclose power semiconductor device, wherein the bulk material of the thin film layer comprises an imide-based, ethylene-based, propylene-based polymer, or a combination thereof.
However, Orita discloses a passivation film for semiconductor devices such as solar cells, wherein the bulk material of the thin film layer comprises an imide-based “polyimide” [0349], ethylene-based [0088] or a combination thereof.
Therefore, it would have been obvious for one of ordinary skill in the art, prior to the effective filing date of the instant application, to use similar imide-based compound such as polyimide in order to achieve the desired isolation of the base material of the semiconductor chip from external and corrosive environment.
Although Orita disclosure does not specify polyimide as being UV curable, examiner takes an Official Notice that UV curable polyimide is well-known in the art as a passivation for semiconductor devices.
Therefore, it would have been obvious for one of ordinary skill in the art, prior to the effective filing date of the instant application, to use similar UV curable imide-based compound such as UV curable polyimide in order to achieve the desired isolation of the base material of the semiconductor chip from external and corrosive environment with minimum thermal budget.
RE Claim 6, BEYER does not disclose power semiconductor device, wherein the laminar filler compound of the thin film layer has a hydrophobic-modified surface.
However, in a related art, Orita discloses a passivation film for semiconductor devices such as solar cells, made of polymer compound have anionic group or a cationic group and a filler [abstract and 0021-0029], wherein the passivation film comprising a bulk material made of polyfluoroolefin resin and a filler comprising montmorillonite, which inherently has hydrophobic-modified surface.
Therefore, it would have been obvious for one of ordinary skill in the art, prior to the effective filing date of the instant application to use the montmorillonite, as the thin film filler due to its well-known hydrophobic-modified surface in order to best protective properties of the edge-termination region of BEYER disclosed device.
RE Claim 9, BEYER in view of Orita do not disclose power semiconductor device, wherein the content of the laminar filler compound in the thin film layer is at least 0.5 wt.-% and at most 5 wt.-%.
However, it would have been obvious to one having ordinary skill in the art prior to the effective filing date of the instant application to use the claimed laminar filler weight percentages, absent unexpected results, since it has been held that discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233; In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980); In re Huang, 100 F.3d 135, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996).
Claim(s) 6 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over BEYER et al. (EP-3951841), (hereinafter, BEYER) in view of Orita et al. (US 2012/0313199), (hereinafter, Orita) and in further view of Dulebova et al. (“Properties and Application of Polymer-Clay Nanocomposites,” American Journal of Polymer Science, 5(2): 47-53, 2015), (hereinafter, Dulebova).
RE Claim 6, BEYER in view of Orita disclose power semiconductor device, wherein the laminar filler compound of the thin film layer is montmorillonite, which is considered hydrophobic surface.
However, if applicant proof that montmorillonite does not has a hydrophobic-modified surface, it would have been obvious for one of ordinary skill in the art, prior to the effective filing date of the instant applicant in view of the related art of Dulebova disclosure, which discloses nano-clay polymer composites wherein the surface of the nanoclay surface to be hydrophobically modified [section 2] in order to have ordered layered nanoclay composited without voids or gaps as disclosed by Dulebova [introduction].
RE Claim 7, BEYER in view of Orita do not disclose power semiconductor device, wherein the thin film layer comprises the laminar filler compound in a laminar structure in which the laminar filler compound is oriented substantially parallel to a surface of the power semiconductor device.
However, in a related art, Dulebova discloses polymer-nanoclay composites and methods of making the same with controlled structure, wherein nano-clay composites are made of lattice structure with sheets comprising two-dimensional layers wherein octahedral layer of aluminum or magnesium is surrounded by external tetrahedral layers, which implies parallel layer.
Therefore, it would have been obvious for one of ordinary skill in the art, prior tot the effective filing date of the instant application to have the laminar filler compound in a laminar structure in which the laminar filler compound is oriented substantially parallel to a surface of the power semiconductor device of BEYER in view of Orita in order to achieve no gaps or voids in the composited structure to structural strength and enhance the barrier capabilities of the passivation film.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over BEYER et al. (EP-3951841), (hereinafter, BEYER) in view of Orita et al. (US 2012/0313199), (hereinafter, Orita) and in further view of Saedi (“Intercalated Polyamide-Imide Nanocomposite with Montmorillonite,” American Journal of Polymer Science, 5(2): 47-53, 2015), (hereinafter, Saedi).
RE Claim 8, BEYER in view of Orita do not disclose power semiconductor device, wherein the laminar filler compound of the thin film layer comprises a layered silicate.
However, in a related art, Saedi discloses nanoclay-polymer composites, wherein fillers such as layered polymer-silicate, i.e. layered silicate “laminar” filling the polymer composite is well-known in the art [first page, right-hand column, second paragraph].
Therefore, it would have been obvious for one of ordinary skill in the art, prior to the effective filing date of the instant application, to use the layered silica as the laminar filler of the BEYER in view of Orita thin film in order to improve the barrier properties of the thin film passivation layer that termination end region “TR”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YASSER ABDELAZIEZ whose telephone number is (571)270-5783. The examiner can normally be reached Monday - Friday 9 am - 6 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at (571)270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YASSER A ABDELAZIEZ, PhD/Primary Examiner, Art Unit 2898