DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species II in the reply filed on 2/20/26 is acknowledged. The traversal is on the ground(s) that independent claims 1 and 21 both recite fence patterns, and the identifiers of Examiner-identified species I and II are not mutually exclusive to Examiner Identified species I. This is found to be persuasive, Species I and III will be examined, identified as Claims 1-5, 7-13, 21-23. Claims 14, 15, 18-20 are considered withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 7-13, 21-23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Son et al US 2021/0134809, and further in view of Lee et al US 2023/0005935.
Pertaining to claim 1, Son teaches a semiconductor device comprising:
a first active pattern 104 and a second active pattern 104 extending in a first direction and adjacent to each other in a second direction, the second direction intersecting the first direction, the first and second active patterns, each including a first edge portion and a second edge portion spaced apart from each other in the first direction See Figure 1B [0019][0031-0035];
a first storage node pad 415 and a first storage node contact 417+418 sequentially provided on the first edge portion of the first active pattern;
a second storage node pad 415 and a second storage node contact 417+418 sequentially provided on the second edge portion of the second active pattern; and
a fence pattern 124 see Figure 1D between the first storage node contact and the second storage node contact,
a bottom surface and a top surface of the first storage node contact located at a first level and a second level See Figure 1B and Figure 1D, respectively.
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Son fails to teach wherein a width of the fence pattern in a third direction, the third direction intersecting the first and second directions, the width of the fence pattern at the first level being less than a width of the fence pattern in the third direction at the second level. Son teaches the top narrower than the bottom. Lee teaches a fence in an analogous device wherein the fence has the top wider than the bottom see Figure 14 marked up below. It would have been within the scope of one of ordinary skill in the art at the time the invention was filed to combine the teachings of Son and Lee to enable the fence formation step of Son to be performed according to the teachings of Lee because one of ordinary skill in the art at the time the invention was filed would have been motivated to look to alternative suitable methods of performing the disclosed fence formation step of Son and art recognized suitability for an intended purpose has been recognized to be motivation to combine. MPEP § 2144.07.
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Pertaining to claim 2, Son in view of Lee teaches the semiconductor device of claim 1, wherein a width of the fence pattern in the third direction decreases as a level decreases. Lee teaches that the fence tapers, see Figure 14
Pertaining to claim 3, Son in view of Lee teaches the semiconductor device of claim 1, wherein the first storage node pad 415 includes a same material as the first storage node contact 417+418. Both can include Titanium see [0040] of Son
Pertaining to claim 4, Son in view of Lee teaches the semiconductor device of claim 1, wherein the first storage node contact includes dopant-doped poly-silicon. Lee teaches a storage node contact 184b that includes dopant-doped poly-silicon see [0114] and Figure 35
Pertaining to claim 5, Son in view of Lee teaches the semiconductor device of claim 1, wherein the fence pattern 124 is in contact with the first storage node contact 417+418 and the second storage node contact 417+418. See Son Figure 2A
Pertaining to claim 7, Son in view of Lee teaches the semiconductor device of claim 1, wherein
each of the first active pattern 104 and the second active pattern 104 further includes a center portion between the first edge portion and the second edge portion (see figure 1B marked up above), and
the center portion of the first active pattern and the center portion of the second active pattern are sequentially arranged in the second direction. See Figure 1A of Son
Pertaining to claim 8, Son in view of Lee teaches the semiconductor device of claim 1, wherein
each of the first active pattern 104 and the second active pattern 104 further includes a center portion between the first edge portion and the second edge portion (see figure 1B marked up above), and
the semiconductor device further comprising:
a bit line node pad 312 provided on each of the center portions of the first and second active patterns See Son Figure 1A element 314 (BL) and Figure 1B element BLS which includes 314/312 and BL.
Pertaining to claim 9, Son in view of Lee teaches the semiconductor device of claim 1, further comprising:
a first bit line extending in the third direction on the first active pattern; and a second bit line extending in the third direction on the second active pattern,
wherein the first storage node contact and the second storage node contact are disposed between the first bit line and the second bit line. See Son Figure 1A element 314 (BL)
Pertaining to claim 10, Son in view of Lee teaches the semiconductor device of claim 9, wherein the fence pattern 124 (Son) has a rounded corner between the first bit line and the second bit line when viewed in a plan view. Son teaches a fence with a rounded corner See Figure 6C in conjunction with Figure 1A
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Pertaining to claim 11, Son in view of Lee teaches the semiconductor device of claim 1, further comprising:
a third active pattern 104 Figure 1B of Son (there are many adjacent 104 patterns as illustrated in Figure 1A which shows many Figure 1B elements adjacent to each other in rows) adjacent to the second active pattern in the third direction,
wherein the third active pattern includes a first edge portion and a second edge portion spaced apart from each other in the first direction see Figure 1A, and
wherein the second edge portion of the third active pattern is adjacent to the first edge portion of the first active pattern See Figure 1A which shows that there are a plurality of these all arrayed.
Pertaining to claim 12, Son in view of Lee teaches the semiconductor device of claim 11, further comprising:
a third storage node pad and a third storage node contact sequentially provided on the second edge portion of the third active pattern,
wherein the second storage node contact, the first storage node contact and the third storage node contact are arranged in a line in the third direction Again, see Figure 1A that shows the plan view of the device, illustrating repeat pattern of what is shown in Figure 1B.
Pertaining to claim 13, Son in view of Lee teaches the semiconductor device of claim 11, further comprising:
a dummy word line WL [0022][0031][0034] extending in the second direction between the second active pattern and the third active pattern See Figure 1A in conjunction with Figure 1C/1D.
Pertaining to claim 21, Son teaches a semiconductor device comprising:
a first active pattern and a second active pattern extending in a first direction and adjacent to each other in a second direction, the second direction intersecting the first direction, the first and second active patterns, each of including first and second edge portions spaced apart from each other in the first direction and a center portion between the first and second edge portions; See Figure 1B marked up below and Figure 1A for plan view
a pair of word lines extending in the second direction to intersect the first active pattern and the second active pattern See Figure 1D marked up below;
a first storage node pad 415 and a first storage node contact 417+418 sequentially provided on the first edge portion of the first active pattern; See Figure 1B
a second storage node pad 415 and a second storage node contact 417+418 sequentially provided on the second edge portion of the second active pattern; See Figure 1B
a first bit line extending in a third direction, the third direction intersecting the first and second directions, on the first active pattern; See element BLS (BL) Figure 1B and Figure 1A
a second bit line extending in the third direction on the second active pattern Figure 1A illustrates multiple bit lines BL;
a fence pattern 124 between the first storage node contact and the second storage node contact;
landing pads 418c [0038] on the first storage node contact and the second storage node contact; and
data storage patterns CAP on the landing pads [0044],
a bottom surface and a top surface of the first storage node contact located at a first level and a second level, respectively, and
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a width of the fence pattern in the third direction at the first level being less than a width of the fence pattern in the third direction at the second level.
Son fails to teach wherein a width of the fence pattern in the third direction at the first level being less than a width of the fence pattern in the third direction at the second level. Son teaches the top narrower than the bottom see Figure 14 marked up below. Lee teaches a fence in an analogous device wherein the fence has the top wider than the bottom. It would have been within the scope of one of ordinary skill in the art at the time the invention was filed to combine the teachings of Son and Lee to enable the fence formation step of Son to be performed according to the teachings of Lee because one of ordinary skill in the art at the time the invention was filed would have been motivated to look to alternative suitable methods of performing the disclosed fence formation step of Son and art recognized suitability for an intended purpose has been recognized to be motivation to combine. MPEP § 2144.07.
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Pertaining to claim 22, Son in view of Lee teaches the semiconductor device of claim 21, wherein each of the landing pads 418c includes a lower portion and an upper portion, and the upper portion of each of the landing pads is shifted from the lower portion in the third direction or an opposite direction to the third direction See Figure 1B.
Pertaining to claim 23, Son in view of Lee teaches the semiconductor device of claim 21, further comprising:
a third active pattern adjacent to the second active pattern in the third direction; and
a fourth active pattern adjacent to the first active pattern in the third direction,
wherein each of the third active pattern and the fourth active pattern includes a first edge portion and a second edge portion spaced apart from each other in the first direction; and a center portion between the first and second edge portions, and the first bit line further extends onto the center portion of the fourth active pattern, and wherein the second bit line further extends onto the center portion of the third active pattern. This repeated pattern is illustrated by Son in Figure 1A (the plan view) showing that these elements and patterns repeat as indicated by the wavy lines at the boundaries of the Figure. Figure 1A shows at least 4 of such elements regardless.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS J TOBERGTE whose telephone number is (571)272-6458. The examiner can normally be reached M-F 7:30-4:30.
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/NICHOLAS J TOBERGTE/Primary Examiner, Art Unit 2817
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