DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5 and 9-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hiraga et al. (WO 2019168187) (“Hiraga”).
With regard to claim 1, figs. 27-31 of Hiraga discloses a method for manufacturing an image display device, the method comprising: forming, on a substrate 1006, a layer 1002 comprising a first part made of a single-crystal (“first buffer layer 1002 is a single crystal”, par [0032]) metal (“metal”, par [0033]); forming a semiconductor layer (1003a, 1003b, 1003c) on the first part 1007, the semiconductor layer (1003a, 1003b, 1003c) comprising a light-emitting layer 1003b; forming a light-emitting element (1003a, 1003b, 1003c) by patterning the semiconductor layer (1003a, 1003b, 1003c), the light-emitting element (1003a, 1003b, 1003c) comprising: a light-emitting surface (bottom of 1003a, fig. 28) on the first part 1003a, and an upper surface at a side (top of 1003c) opposite to the light-emitting surface (bottom 1003a); forming a first insulating film 1025 that covers the substrate 1006, the layer 1002 that comprises the first part 1002, and the light-emitting element (1003a, 1003b, 1003c); forming a circuit element (1020, 1022) on the first insulating film 1025; forming a light-shielding member 1004 between the circuit element (1020, 1022) and the light-emitting element (1003a, 1003b, 1003c); forming a second insulating film 1026 covering the first insulating film 1025 and the circuit element (1020, 1022); forming a first via (vertical portion of 1024 touching 1004) extending through the first 1025 and second insulating films 1026; forming a wiring layer (horizontal portion of 1024) on the second insulating film 1026; removing (“peeling the non-oriented substrate 1006”, par [0132]) the substrate 1006; and removing (“peeling”, par [0132]) at least a portion of the first part (“first buffer layer 1002”, par [0132]) on the light-emitting surface (bottom of 1003a), wherein: the first via 1024 is located between the wiring layer (horizontal portion of 1024) and the upper surface (top of 1003c) and electrically connecting 1024 the wiring layer (horizontal portion of 1024) and the upper surface (top of 1003c).
With regard to claim 2, figs. 27-31 of Hiraga discloses that the forming of the layer 1002 including the first part 1002 includes: forming a metal layer 1002 on the substrate 1006; and forming the first part 1002 by performing annealing treatment (“annealing”, par [0119]) of the metal layer 1002, an outer perimeter of the light-emitting element (1003a, 1003b, 1003c) is located within an outer perimeter of the first part 1002 when viewed in plan.
With regard to claim 3, figs. 27-31 of Hiraga discloses that the forming of the layer that includes the first part 1002 comprises, before the annealing treatment (“annealing”, par [0119]) of the metal layer 1002, patterning the metal layer 1002.
With regard to claim 4, figs. 27-31 of Hiraga discloses that the forming of the light-shielding member 1004 comprises forming a light-shielding electrode 1004 on the upper surface (top of 1003c), and the first via (vertical portion of 1024 touching 1004) is electrically connected to the upper surface (top of 1003c) via the light-shielding electrode 1004.
With regard to claim 5, figs. 27-31 of Hiraga discloses that the forming of the light-shielding member 1004 comprises forming a light-shielding layer 1004 on the first insulating film 1005 before the forming of the circuit element (1020, 1022).
With regard to claim 9, figs. 27-31 of Hiraga discloses that the semiconductor layer 1003 comprises a gallium nitride (“GaN”, par [0134]) compound semiconductor.
With regard to claim 10, figs. 27-31 of Hiraga discloses after the removing of the substrate (“peeling the non-oriented substrate 1006”, par [0132]), forming a wavelength conversion member 1008C on the light-emitting surface (bottom of 1003a).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Hiraga et al. (WO 2019168187) (“Hiraga”) in view of Takeya et al. (US 2019/0229097) (“Takeya”).
With regard to claim 6, Hiraga does not disclose forming a second via extending through the first and second insulating films, wherein: the light-emitting element comprises a first connection part located along the light-emitting surface, the second via is located between the wiring layer and the first connection part and electrically connects the wiring layer and the first connection part.
However, fig. 2 of Takeya discloses forming a second via 170 extending through the first (bottom part of 163) and second insulating films (top part of 163), wherein: the light-emitting element (157, 155, 153) comprises a first connection part 159b located along the light-emitting surface 153, the second via 170 is located between the wiring layer 171d and the first connection part 159p and electrically connects the wiring layer 171d and the first connection part 159p.
Therefore, it would have been obvious to one of ordinary skill in the art to form the LED of Hiraga with the first electrode as taught in Takeya in order to provide both electrical connections to the LED on one side of the LED. See par [0127]) of Takeya.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Hiraga et al. (WO 2019168187) (“Hiraga”) in view of Kong et al. (US 2021/0091279) (“Kong”).
With regard to claim 7, Hiraga does not disclose after removing the at least a portion of the first part on the light-emitting surface, roughening the exposed light-emitting surface.
However, fig. 19 of Kong discloses that after removing (“substrate 100 may be removed”, par [0174]) the at least a portion of the first part on the light-emitting surface, roughening 700 the exposed light-emitting surface.
Therefore, it would have been obvious to one of ordinary skill in the art to form the back of the Led of Hiraga with the extraction pattern as taught in Kong in order to increase the emission efficiency of the light emitted from the light emitting device. See par [0179] of Kong.
Allowable Subject Matter
Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN T LIU whose telephone number is (571)272-6009. The examiner can normally be reached Monday-Friday 11:00am-7:30pm.
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/BENJAMIN TZU-HUNG LIU/Primary Examiner, Art Unit 2893