DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10, 21-30 are rejected under 35 U.S.C. 103 as being unpatentable over Yuh et al (US Publication No. 2023/0067715) and Cheng et al (US Publication No. 2022/0052206).
Regarding claims 1 and 21, Yuh discloses an apparatus and a method comprising a transistor, the transistor comprising: a drain Fig 17, 190 ¶0074 including a first drain silicide layer Fig 17, 240 ¶0075 on a frontside surface of the drain and a second drain silicide layer Fig 17, 350 ¶0085 on a backside surface of the drain, wherein at least one of the first drain silicide layer Fig 17, 350 is coupled to a first drain contact structure Fig 17, 250 or the second drain silicide layer is coupled to a second drain contact structure Fig 17, 360; a source Fig 17, 190 ¶0074 including a first source silicide layer Fig 17, 240 ¶0075 on a frontside surface of the source and a second source silicide layer on a backside surface of the source Fig 24 ¶0111, wherein at least one of the first source silicide layer is coupled to a first source contact structure or the second source silicide layer is coupled to a second source contact structure; a gate structure disposed between the source and the drain ¶0111; and a channel Fig 24, 122 at least partially enclosed by the gate structure Fig 24, 220 and disposed between the source and the drain Fig 24. Yuh discloses all the limitations but silent on the recessed channel. Whereas Cheng discloses wherein the channel is recessed from the backside surface of the source and the backside surface of the drain Fig 19A-19D ¶0059.
Yuh and Cheng are analogous art because they are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Yuh because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Yuh and incorporate the teachings of Cheng to improve efficiency and scaling ¶0002.
Regarding claims 2 and 22, Cheng discloses wherein the channel is recessed in a range of 5 nanometers to 50 nanometers from the backside surface of the source and the backside surface of the drain ¶0026.
Regarding claims 3 and 23, Cheng discloses : a fill dielectric Fig 20D, 376 disposed between the source and the drain, wherein the fill dielectric extends from the channel to the backside surface of the source and the backside surface of the drain Fig 20A-20D ¶0060.
Regarding claims 4 and 24, Yuh discloses, wherein a metal gate of the gate structure is coupled, by a gate frontside contact structure, to a first frontside metallization layer of a frontside metallization structure, or the metal gate is coupled, by a gate backside contact structure, to a first backside metallization layer of a backside metallization structure ¶0123-0129.
Regarding claims 5 and 25, Yuh discloses a frontside metallization structure having one or more frontside metallization layers, wherein at least one of: the first drain contact structure is coupled to a first drain connection portion of the frontside metallization structure in a first frontside metallization layer, or the first source contact structure is coupled to a first source connection portion of the frontside metallization structure in the first frontside metallization layer Fig 13-27.
Regarding claims 6 and 26, Yuh discloses a backside metallization structure having one or more backside metallization layers, wherein at least one of: the second drain contact structure is coupled to a second drain connection portion of the backside metallization structure in a first backside metallization layer, or the second source contact structure is coupled to a second source connection portion of the backside metallization structure in the first backside metallization layer Fig 23-27.
Regarding claims 7 and 27, Yuh discloses wherein the transistor is a fin field-effect transistor (FinFET) or a Gate-All-Around (GAA) transistor ¶0069 Fig 10A.
Regarding claims 8 and 28, Yuh discloses wherein the FinFET comprises a plurality of fins ¶0048-0049 Fig 5A.
Regarding claims 9 and 29, Yuh discloses wherein the drain comprises a plurality of drains each grown epitaxially on one of the plurality of fins and wherein the second drain silicide layer is disposed between drains on adjacent fins of the plurality of fins, and wherein the source comprises a plurality of sources each grown epitaxially on one of the plurality of fins and wherein the second source silicide layer is disposed between sources on adjacent fins of the plurality of fins ¶0060-0062, 0075,0085-0086.
Regarding claims 10 and 30, Yuh discloses wherein the apparatus comprises at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of Things (IoT) device, a laptop computer, a server, an access point, a base station, or a device in an automotive vehicle ¶0001.
Claims 11-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hung et al (US Publication No. 2022/0271026) in view of Cheng et al (US Publication No. 2022/0052206) and Yuh et al (US Publication No. 2023/0067715).
Regarding claim 11, Hung discloses an apparatus, comprising: a plurality of frontside lines Fig 7, 169; a plurality of backside lines Fig 7, 157; a first diffusion region extending in a first direction ¶0026-0027; a second diffusion region extending in the first direction¶0032-0033; a plurality of gate structures Fig 7; and a first transistor comprising: a first source and a first drain disposed in one of the first diffusion region and the second diffusion region Fig 7; a first gate structure, disposed in one of the plurality of gate structures and disposed between the first source and the first drain Fig 7; and a first channel Fig 7, disposed between the first source and the first drain Fig 7. Hung discloses all the limitations but silent on the arrangement of the gate structure. Whereas Cheng discloses a plurality of gate structures Fig 6A-6D offset from each other in the first direction and extending in a second direction perpendicular to the first direction Fig 6A-6D; and a first transistor comprising: a first source and a first drain Fig 7A-7D; a first gate structure, disposed in one of the plurality of gate structures and disposed between the first source and the first drain Fig 7A-7D; and a first channel Fig 7A-7D, at least partially enclosed by the first gate structure Fig 7A-7D, and disposed between the first source and the first drain Fig 7A-7D, wherein the first channel is recessed from a backside surface of the first source and a backside surface of the first drain Fig 19A-19D. Hung and Cheng are analogous art because they are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Hung because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Hung and incorporate the teachings of Cheng to improve efficiency and scaling ¶0002.Hung and Cheng discloses all the limitations but silent on the interconnects. Whereas Yuh discloses wherein at least one of the first gate structure, the first source, or the first drain is coupled to a first backside line of the plurality of backside lines Fig 23-27. Hung and Yuh are analogous art because they are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Hung because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Hung and incorporate the teachings of Yuh to improve device interconnect.
Regarding claim 12, Yuh discloses wherein the first gate structure further comprises a metal gate coupled to a first gate via coupled to one of the plurality of backside lines Fig 26A-Fig 33.
Regarding claim 13, Cheng discloses wherein the first gate structure further comprises a metal gate coupled to a first gate via coupled to one of the plurality of frontside lines ¶0040,0049, 0062.
Regarding claim 14, Yuh discloses one or more backside interconnects disposed adjacent to the plurality of backside lines Fig 26A-Fig 33.
Regarding claim 15, Yuh discloses wherein the first source is coupled to the first backside line through one of the one or more backside interconnects Fig 26A-Fig 33.
Regarding claim 16, Yuh discloses wherein the first drain is coupled to the first backside line through one of the one or more backside interconnects Fig 26A-Fig 33.
Regarding claim 17, Yuh discloses wherein the first backside line is coupled to a first power source at a positive potential and a second backside line of the plurality of backside lines is coupled to a second power source at a ground or negative potential Fig 35A -41 ¶0134-0135.
Regarding claim 18, Yuh discloses a frontside metallization structure having a plurality of frontside metallization layers, wherein a first frontside metallization layer comprises the plurality of frontside lines; and a backside metallization structure having a plurality of backside metallization layers, wherein a first backside metallization layer comprises the plurality of backside lines Fig 26A-Fig 33.
Regarding claim 19, Yuh discloses wherein at least one of: the first drain includes a first drain silicide layer on a frontside surface of the first drain and a second drain silicide layer on a backside surface of the first drain, wherein the second drain silicide layer is coupled to a second drain contact structure coupled to one of the plurality of backside lines; or the first source includes a first source silicide layer on a frontside surface of the first source and a second source silicide layer on the backside surface of the first source, wherein the second source silicide layer is coupled to a second source contact structure coupled to one of the plurality of backside lines Fig 26A-Fig 33.
Regarding claim 20, Yuh discloses a plurality of tracks each of which comprise one or more of the plurality of frontside lines, wherein the plurality of tracks is two or three tracks Fig 26A-Fig 33.
Conclusion
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/CHRISTINE A ENAD/Primary Examiner, Art Unit 2811