DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6 is/are rejected under 35 U.S.C. 102(a1) as being anticipated by Takaki et al., (Takaki) US 2016/0233270.
Regarding claim 1, Takaki discloses and shows in FIG. 1A-5O, a memory device configured as a dynamic random-access memory [0015], the memory device comprising: a substrate [0020] supporting a first semiconductor device layer comprising a first bit cell (108a)[0026]; a second semiconductor device layer comprising a second bit cell (108b1), wherein the first semiconductor device layer is arranged vertically between the substrate and the second semiconductor device layer, wherein each of the first and second bit cells (108) includes a write transistor and a read transistor [0027], and wherein a first source/drain terminal (connected to 205a) or (111) of the write transistor is connected to a gate (201)of the read transistor to form a storage node of each of the first and second bit cells; a first interconnecting structure (113)[0022] extending vertically between the first and second semiconductor device layers and being arranged to form a write word line common to gate terminals of the write transistors of the first and second bit cells (see FIG. 1B); and a second interconnecting structure (113 on opposite side) extending vertically between the first and second semiconductor device layers and being arranged to form a read word line common to first source/drain terminals (111 or 205) of the read transistors of the first and second bit cells.
Regarding claim 2, Takaki discloses and shows in FIG. 1A-5O, a memory device wherein each of the first and second semiconductor device layers (108) comprises a plurality of bit cells [0028] and a horizontal read bit line interconnecting a second source/drain terminal (11, or 205) of the read transistors of each of the first and second bit cells.
Regarding claim 3, Takaki discloses and shows in FIG. 1A-5O, a memory device wherein each of the first and second semiconductor layers (108) further comprises a horizontal write bit line [0027] interconnecting the second source/drain terminal (111 or 205) of the write transistors of each bit cell.
Regarding claim 4, Takaki discloses and shows in FIG. 1A-5O, a memory device wherein the horizontal read bit line [0027] of the first semiconductor device layer is electrically insulated from the horizontal read bit line of the second semiconductor device layer (108).
Regarding claim 5, Takaki discloses and shows in FIG. 1A-5O, a memory device wherein the horizontal write bit line [0027] of the first semiconductor device layer (108a) is electrically insulated from the horizontal write bit line of the second semiconductor device layer (108b1).
Regarding claim 6, Takaki discloses and shows in FIG. 1A-5O, a memory device wherein the write transistor [0027] and the read transistor are metal-oxide semiconductor field-effect transistors [0027](could be TiO, ZrO …).
Allowable Subject Matter
Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed 7/10/26 have been fully considered but they are not persuasive.
Applicant argues that “Takaki is not even directed to "a memory device configured as a dynamic random-access memory".” The Examiner respectfully disagrees because “dynamic random-access memory” is part of the preamble.
With respect to “dynamic random-access memory”, that has not been given patentable weight because it have been held that a preamble is denied the effect of a limitation where the claim is drawn to a structure and the portion of the claim following the preamble is a self-contained description of the structure not depending for completeness upon the introductory clause, MPEP 2111.02.
Applicant argues that “Takaki does not teach a first semiconductor device layer or a second semiconductor device layer.” The Examiner respectfully disagrees because Takaki discloses [0047,0118] a first semiconductor device layer or a second semiconductor device layer.
Applicant argues that “Takaki's memory cell region 102 fails to reasonably correspond to the "first and second bit cells" "wherein each of the first and second bit cells includes a write transistor and a read transistor".” The Examiner respectfully disagrees because Takaki discloses [0068] a device having a first and second bit cells wherein each of the first and second bit cells includes a write transistor and a read transistor.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARC-ANTHONY ARMAND whose telephone number is (571)272-5178. The examiner can normally be reached 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven B Gauthier can be reached at 571-270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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MARC - ANTHONY ARMAND
Primary Examiner
Art Unit 2813
/MARC-ANTHONY ARMAND/Primary Examiner, Art Unit 2813
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