DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “INTERCONNECT STRUCTURE AND METHOD OF FORMING THE SAME”.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 17-20 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 17 recited “a first etch stop layer exposed by the opening” in line 14. The examiner is confused if a first etch stop layer in line 14 is same layer as a first etch stop layer in line 4 or different layer. If a first etch stop layer in line 14 is same layer as a first etch stop layer in line 4 then the examiner suggests changing to “the first etch stop layer exposed by the opening”. For examination purpose, the examiner consider that a first etch stop layer in line 14 is same layer as a first etch stop layer in line 4.
Claims 18-20 depends on the independent claim 17 so they are rejected for the same reason.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ishizaka et al. (US Patent No. 7,727,883) in view of Kloster et al. (US Patent Appl. Pub. No. 2002/0140103 A1).
[Re claim 1] Ishizaka discloses the interconnect structure, comprising: a first conductive feature (122) in a first dielectric layer (114); a first etch stop layer (116) over the first conductive feature and the first dielectric layer; a second dielectric layer (118) on the first etch stop layer; and a second conductive feature (134) electrically connecting the first conductive feature, wherein the second conductive feature comprises; a first conductive layer (134) extending through the second dielectric layer (118), and the first etch stop layer (116) to contact to the first conductive feature; and a first barrier layer (132) sandwiched between the first conductive layer (134) and the second dielectric layer (118), and between the first conductive layer (134) and the first etch stop layer (116) (see figure 1A-1J and column 3 line 30 through column 6 line 36). However, Ishizaka does not disclose the interconnect structure comprising a second etch stop layer on the first etch stop layer. Kloster discloses the interconnect structure comprising a second etch stop layer (18) on the first etch stop layer (16) (see figure 1 and paragraph [0023]). It would have been obvious to one of ordinary skill in the art to the effective filing date of the instant application to have a second etch stop layer on the first etch stop layer in the device of Ishizaka in order to give extra protection from etching second dielectric layer.
[Re claim 2] Ishizaka also discloses the interconnect structure wherein the second conductive feature comprises a via (128) and a conductive line (area where 126 is located) on the via (see figure 1A and 1J).
[Re claim 3] Ishizaka also discloses the interconnect structure wherein sidewalls of the first conductive layer (134) of the via are separated from the first etch stop layer (116) by the first barrier layer (132) (see figure 1J).
[Re claim 4] Kloster also discloses the interconnect structure wherein the first etch stop layer (16) and the second etch stop layer (18) have different materials, and the first etch stop layer comprises a Group IV element-doped layer (see paragraphs [0031]-[0034]).
[Re claim 5] Kloster also discloses the interconnect structure wherein a material of the Group IV element-doped layer comprises carbon-doped metal oxide, carbon-doped metal nitride, metal carbide, semiconductor carbide, semiconductor carbon nitride, semiconductor carbon oxide, or a combination thereof (see paragraphs [0031]-[0034]).
[Re claim 6] Ishizaka also discloses the interconnect structure wherein a bottom surface of the first conductive layer (134) of the via is in physical contact with a top surface of the first conductive feature (122) (see figure 1J and column 6 lines 20-27).
[Re claim 7] Ishizaka also discloses the interconnect structure wherein the first conductive feature comprises a second conductive layer (122) and a second barrier layer (120) surrounding the second conductive layer (see figure 1A and column 3 lines 30-49).
Claim(s) 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ishizaka et al. (US Patent No. 7,727,883) in view of Kloster et al. (US Patent Appl. Pub. No. 2002/0140103 A1) and Hsueh et al. (US Patent No.11,362,035).
[Re claim 8] The combined teaching of Ishizaka and Kloster discloses as claimed and rejected in claim 7 and Ishizaka also discloses the interconnect structure wherein a top surface of the second conductive layer (122) of the first conductive feature is in contact with a bottom surface of the first conductive layer (134) of the via (see fig. 1J). However, the combined teaching of Ishizaka and Kloster does not disclose the interconnect structure wherein a top surface of the second barrier layer of the first conductive feature is in contact with a bottom surface the first barrier layer of the via. Hsueh discloses the interconnect structure wherein a top surface of the second barrier layer (108) of the first conductive feature is in contact with a bottom surface the first barrier layer (118) of the via (see figure 4A). It would have been obvious to one of ordinary skill in the art to the effective filing date of the instant application to a top surface of the second barrier layer of the first conductive feature is in contact with a bottom surface the first barrier layer of the via in the device of Ishizaka in order to completely surround the first and second conductive feature with a barrier layer.
[Re claim 9] Hsueh also discloses the interconnect structure further comprising: a third etch stop layer (306) disposed between the second dielectric layer (104b) and the second etch stop layer (304), wherein the third etch stop layer (306) and the second etch stop layer (304) have different materials (see figure 4A and column 5 line 59-67).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 10-11 and 14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ishizaka et al. (US Patent No. 7,727,883).
[Re claim 10] Ishizaka discloses the interconnect structure, comprising: a conductive feature (122) disposed in a first dielectric layer (114); a second dielectric layer (118) disposed over the first dielectric layer; an etch stop stack (116) inserted between the first dielectric layer and the second dielectric layer; a conductive line (134) disposed in the second dielectric layer and the etch stop stack, wherein the conductive line comprises: a first conductive layer (134) disposed in the second dielectric layer (118) and the etch stop stack (116) a first barrier layer (132) extending from a top of the second dielectric layer to a bottom of the etch stop stack, wherein the first conductive layer is laterally surrounded by the first barrier layer and in contact with the conductive feature (see figure 1A-1J and column 3 line 30 through column 6 line 36).
[Re claim 11] Ishizaka also discloses the interconnect structure wherein the first barrier layer (132) separates the first conductive layer (134) from the second dielectric layer (118) and the etch stop stack (116) (see figure 1J).
[Re claim 14] Ishizaka also discloses the interconnect structure wherein the conductive feature comprises a second conductive layer (122) and a second barrier layer (120) surrounding the second conductive layer (see figure 1A and column 3 lines 30-49).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ishizaka et al. (US Patent No. 7,727,883) in view of Tung et al. (US Patent Appl. Pub. No. 2018/0005876 A1).
[Re claim 12] Ishizaka discloses the interconnect structure as claimed and rejected in claim 10, but Ishizaka does not disclose the interconnect structure comprising a second etch stop layer on the first etch stop layer. Tung discloses the interconnect structure comprising a second etch stop layer (109) on the first etch stop layer (108) (see figure 9B-9G and paragraph [0041]-[0042]). It would have been obvious to one of ordinary skill in the art to the effective filing date of the instant application to have a second etch stop layer on the first etch stop layer in the device of Ishizaka in order to give extra protection from etching second dielectric layer.
[Re claim 13] Tung also discloses the interconnect structure wherein the first barrier layer (120A and 120B) covers sidewalls of the first etch stop layer (108) and the second etch stop layer (109) (see figure 9G).
Claim(s) 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ishizaka et al. (US Patent No. 7,727,883) in view of Hsueh et al. (US Patent No. 11,362,035).
[Re claim 15] Ishizaka discloses as claimed and rejected in claim 14 and Ishizaka also discloses the interconnect structure wherein the second conductive layer (122) is in contact with the first conductive layer (134) (see fig. 1J). However, Ishizaka does not disclose the interconnect structure wherein the second barrier layer is in contact with the first barrier layer. Hsueh discloses the interconnect structure wherein the second barrier layer (108) is in contact with the first barrier layer (118) (see figure 4A). It would have been obvious to one of ordinary skill in the art to the effective filing date of the instant application to the second barrier layer is in contact with the first barrier layer in the device of Ishizaka in order to completely surround the first and second conductive feature with a barrier layer.
[Re claim 16] Ishizaka also discloses the interconnect structure wherein an interface between a bottom surface of the first conductive layer (134) and a top surface of the second conductive layer (122) is free of the first barrier layer (see figure 1J and column 6 lines 20-27).
Claim(s) 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dutta et al. (US Patent No. 10,879,107) in view of Kloster et al. (US Patent Appl. Pub. No. 2002/0140103 A1).
[Re claim 17] Dutta discloses the method of forming an interconnect structure, comprising: forming a first conductive feature (104) and a first dielectric layer (101), wherein the first dielectric layer surrounds the first conductive feature; forming a first etch stop layer (106) on the first conductive feature and the first dielectric layer; forming a second dielectric layer (108) on the first etch stop layer; forming an opening (135) in the second dielectric layer and the first etch stop layer, wherein the opening exposes a portion of a top surface of the first conductive feature; forming an inhibitor portion (140) on the portion of the top surface of the first conductive feature (104); forming a barrier layer (150) on sidewalls of the second dielectric layer and the first etch stop layer exposed by the opening; removing the inhibitor portion (140); and forming a conductive layer (160) in the opening (see figure 1-8 and column 4 line 22 through column 7 line 59). However, Dutta does not disclose the method wherein forming a second etch stop layer on the first etch stop layer. Kloster discloses the interconnect structure comprising a second etch stop layer (18) on the first etch stop layer (16) (see figure 1 and paragraph [0023]). It would have been obvious to one of ordinary skill in the art to the effective filing date of the instant application to form a second etch stop layer on the first etch stop layer in the method of Dutta in order to give extra protection from etching second dielectric layer.
[Re claim 18] Dutta also discloses the method wherein the inhibitor portion comprises a self-assembled monolayer (140) (see column 6 lines 42-46).
[Re claim 19] Dutta also discloses the method wherein the first etch stop layer (106) comprises a Group IV element-doped layer (see column 4 line 64 through column 7 line 2).
[Re claim 20] Dutta also discloses the method wherein the Group IV element-doped layer comprises AlOxCy, AlxCy, AlxCyNz, TiOxCy, TixCy, TixCyNz, WOxCy, WxCy, WxCyNz, SiOxCy, SiC, SixCyNz or a combination thereof (nitrogen-doped silicon carbide) (see column 4 line 64 through column 7 line 2).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KYOUNG LEE whose telephone number is (571)272-1982. The examiner can normally be reached M to F, 10am to 6pm.
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/KYOUNG LEE/Primary Examiner, Art Unit 2817